A non-volatile memory device and a manufacturing method thereof are provided. The memory device includes a substrate, a lower cell dielectric layer with gate conductors and a body unit conductor disposed on the lower cell dielectric layer and gates. Memory element conductors are disposed on the body unit and lower cell dielectric layer. An upper cell dielectric layer may be on the substrate and over the lower cell dielectric layer, body unit conductor and memory element conductors. The upper cell dielectric layer isolates the memory element conductors.

The present disclosure relates to semiconductor structures and, more particularly, to a vertical memory devices and methods of manufacture. The structure includes: a first bit cell with a first top electrode; a second bit cell with a second top electrode; and a common bottom electrode for both the first bit cell and the second bit cell.

An artificial neuron semiconductor device having a three-dimensional structure includes a first electrode to which a clock signal is applied, a second electrode in which an output signal is generated, an insulation column, a plurality of electrode layers for receiving an electrical signal from at least one synapse circuit, and a phase change layer which is divided into at least two parts by the insulation column and is in contact with at least two side surfaces of the insulation column, and the phase change layer is phase-changed by the plurality of electrode layers.

Resistive memory cells are described. In some embodiments, the resistive memory cells include a switching layer having an inner region in which one or more filaments is formed. In some instances, the filaments is/are formed only within the inner region of the switching layer. Methods of making such resistive memory cells and devices including such cells are also described.

A resistive non-volatile memory cell including a Metal-Insulation-Metal stack including two electrodes and a multilayer of insulation, placed between the two electrodes, including a thin layer of oxide allowing for a resistive transition and an oxygen vacancy reservoir layer is provided. The stack includes from bottom to top: the bottom electrode including a metal layer, the insulation including a layer of stoichiometric metal oxide and a layer of substoichiometric metal oxide forming the oxygen vacancy reservoir layer, and the top electrode including a layer of metal oxide and a metal layer, such that the oxygen vacancy reservoir layer is inserted between two metal oxide stoichiometric layers.

Providing a high-density two-terminal memory architecture(s) having performance benefits of two-terminal memory and relatively low fabrication cost, is described herein. By way of example, the two-terminal memory architecture(s) can be constructed on a substrate, in various embodiments, and comprise two-terminal memory cells formed within conductive layer recess structures of the memory architecture. In one embodiment, a conductive layer recess can be created as a horizontal etch in conjunction with a vertical via etch. In another embodiment, the conductive layer recess can be patterned for respective conductive layers of the two-terminal memory architecture.

The present disclosure provides a 2-dimensional (2D) non-volatile switch (2DNS), with a vertical metal-insulator-metal (MIM) structure that includes a semiconducting monolayer crystalline non-metallic atomic sheet sandwiched between a top metal electrode and a bottom metal electrode. The 2DNS is able to perform stable non-volatile resistance switching, including both unipolar and bipolar switching, with a high ON/OFF ratio, low ON resistance, and low operating voltage. The monolayer atomic sheet may include hexagonal boron nitride (h-BN) or a transition metal dichalcogenide (TMD), such as MoS.sub.2, MoSe.sub.2, WS.sub.2, or WSe.sub.2. The present disclosure also provides methods for synthesizing a semiconducting monolayer crystalline non-metallic atomic sheet on a target substrate. The monolayer atomic sheet may include h-BN or a TMD, such as MoS.sub.2, MoSe.sub.2, WS.sub.2, or WSe.sub.2.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a conductive element disposed within a dielectric structure over the substrate. The conductive element has a top surface extend between outermost sidewalls of the conductive element. A first resistive random access memory (RRAM) element is arranged within the dielectric structure and has a first data storage layer directly contacting the top surface of the conductive element. A second RRAM element is arranged within the dielectric structure and has a second data storage layer directly contacting the top surface of the conductive element.

A switch device including a semiconductor substrate is provided. A trench is formed in the substrate, and a phase change material is provided at least partially in the trench. A heater for heating the phase change material is also provided.

The present disclosure provides a memory structure, including a first interlayer dielectric layer (ILD), a second ILD over the first ILD, wherein at least a portion of an interconnect structure is in the second ILD, a first switch between the first ILD and the second ILD, a second switch over the first switch, and a first phase change material stacking with the first switch and the second switch.