A semiconductor device and method of forming a semiconductor device are provided. The semiconductor device includes a pore-type heater having a center pore recess. The semiconductor device further includes a tapered structure formed on the pore-type heater and having a tip portion at least extending down to the center pore recess. The semiconductor device also includes a containment layer confining volatile active material during any of a fabrication and an operation of the semiconductor device performed above a threshold temperature.

Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a substrate having a pillar protruding from a surface of the substrate, a gate surrounding a part of a side surface of the pillar, a gate dielectric layer, a first electrode, a second electrode, a variable resistance layer, a first doped region and a second doped region. The gate dielectric layer is disposed between the gate and the pillar. The first electrode is disposed on a top surface of the pillar. The second electrode is disposed on the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The first doped region is disposed in the pillar below the gate and in a part of the substrate below the pillar. The second doped region is disposed in the pillar between the gate and the first electrode.

A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a first thermal conducting layer over a bottom electrode, depositing a metal oxide liner over the first thermal conducting layer, forming a second thermal conducting layer over the metal oxide liner, recessing the second thermal conducting layer to expose the first thermal conducting layer, and forming a top electrode in direct contact with the first and second thermal conducting layers.

Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a substrate having a pillar protruding from a surface of the substrate, a gate surrounding a part of a side surface of the pillar, a gate dielectric layer, a first electrode, a second electrode, a variable resistance layer, a first doped region and a second doped region. The gate dielectric layer is disposed between the gate and the pillar. The first electrode is disposed on a top surface of the pillar. The second electrode is disposed on the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The first doped region is disposed in the pillar below the gate and in a part of the substrate below the pillar. The second doped region is disposed in the pillar between the gate and the first electrode.

A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.

A resistance change element includes a first lead electrode, a resistance change layer provided on the first lead electrode, and a second lead electrode provided on the resistance change layer. The surface of the first lead electrode on the resistance change layer side includes a first region in which the resistance change layer is provided, and a second region that is a region other than the first region. In the second region, a second material having a work function that is larger than that of a first material configuring the first lead electrode is unevenly distributed.

A semiconductor storage device includes at least a first electrode layer including a first material; and a memory layer including a second material having a high-resistance state and a low-resistance state switchable based on electric heating. The memory layer has a side surface covered by a side wall layer, the side wall layer including a third material with a higher melting temperature than the second material. The first material has an amorphous structure, a thermal conductivity at least 2-digits lower than a thermal conductivity of a single phase metal, and a resistivity equal to or lower than 50 mΩ.Math.cm and a positive temperature dependence.

A three terminal neuromorphic synaptic device and a method for manufacturing the same are provided. The three terminal neuromorphic synaptic device includes a substrate, source/drain electrodes provided on the substrate, a channel region electrically connected between the source electrode and the drain electrode, an ion transfer layer provided on the channel region, a gate electrode provided on the ion transfer layer, and a voltage application unit to apply a gate voltage to the gate electrode. The ion transfer layer includes an electrolyte material to transfer an active ion of the gate electrode between the gate electrode and the channel region, in response to the gate voltage applied to the gate electrode. The voltage application unit adjusts a resistance and a conductance of the channel region by changing an amount of active ions accumulated in the channel region, depending on the number of times that the gate voltage is applied.

A phase change memory device includes a first electrode, a second electrode, a phase change region, a first spacer and a second spacer. The second electrode is disposed over the first electrode. The phase change region is disposed between the first and second electrodes. The first spacer laterally covers the phase change region. The second spacer laterally covers the first spacer, and has a thermal conductivity smaller than that of the first spacer.

A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.