A wiring substrate includes a ceramic substrate, a thin-film resistor disposed on the ceramic substrate, a first resin layer formed of a resin and disposed in a region on the ceramic substrate where the resistor is not disposed, and a second resin layer formed of a resin and covering the resistor on the ceramic substrate.

A chip resistor includes an upper electrode provided on a substrate, a resistor element connected to the upper electrode, and a side electrode connected to the upper electrode. The side electrode, arranged on a side surface of the substrate, has two portions overlapping with the obverse surface and reverse surface of the substrate, respectively. An intermediate electrode covers the side electrode, and an external electrode covers the intermediate electrode. A first protective layer is disposed between the upper electrode and the intermediate electrode, and held in contact with the upper electrode and the side electrode. The first protective layer is more resistant to sulfurization than the upper electrode. A second protective layer is disposed between the first protective layer and intermediate electrode, and held in contact with the first protective layer, side electrode and intermediate electrode.

A chip resistor includes an upper electrode provided on a substrate, a resistor element connected to the upper electrode, and a side electrode connected to the upper electrode. The side electrode, arranged on a side surface of the substrate, has two portions overlapping with the obverse surface and reverse surface of the substrate, respectively. An intermediate electrode covers the side electrode, and an external electrode covers the intermediate electrode. A first protective layer is disposed between the upper electrode and the intermediate electrode, and held in contact with the upper electrode and the side electrode. The first protective layer is more resistant to sulfurization than the upper electrode. A second protective layer is disposed between the first protective layer and intermediate electrode, and held in contact with the first protective layer, side electrode and intermediate electrode.

A chip resistor includes: a board having a device formation surface, a back surface opposite from the device formation surface and side surfaces connecting the device formation surface to the back surface, a resistor portion provided on the device formation surface, a first connection electrode and a second connection electrode provided on the device formation surface and electrically connected to the resistor portion, and a resin film covering the device formation surface with the first connection electrode and the second connection electrode being exposed therefrom. Intersection portions of the board along which the back surface intersects the side surfaces each have a rounded shape.

A chip resistor includes: a board having a device formation surface, a back surface opposite from the device formation surface and side surfaces connecting the device formation surface to the back surface, a resistor portion provided on the device formation surface, a first connection electrode and a second connection electrode provided on the device formation surface and electrically connected to the resistor portion, and a resin film covering the device formation surface with the first connection electrode and the second connection electrode being exposed therefrom. Intersection portions of the board along which the back surface intersects the side surfaces each have a rounded shape.

The invention is to provide a resistor trimming method capable of adjusting a resistance value with ultrahigh precision and having excellent production efficiency. To achieve the object, a start point (S1) at a distance from a resistor (4) is irradiated with laser light while probes are brought into contact with a pair of surface electrodes (3) to measure a resistance value of the resistor (4). The place irradiated with the laser light is scanned so that a first trimming groove (5) extending in a direction perpendicular to a current direction can be formed in the resistor (4). Then, the place irradiated with the laser light is returned by a predetermined amount from an end point (first turning point (T1)) of the first trimming groove (5) to be set as a second turning point (T2). With the second turning point (T2) as a start point, scanning and cutting is performed to forma second trimming groove (6). Thus, the resistance value of the resistor (4) is adjusted to a target resistance value with high precision.

The invention is to provide a resistor trimming method capable of adjusting a resistance value with ultrahigh precision and having excellent production efficiency. To achieve the object, a start point (S1) at a distance from a resistor (4) is irradiated with laser light while probes are brought into contact with a pair of surface electrodes (3) to measure a resistance value of the resistor (4). The place irradiated with the laser light is scanned so that a first trimming groove (5) extending in a direction perpendicular to a current direction can be formed in the resistor (4). Then, the place irradiated with the laser light is returned by a predetermined amount from an end point (first turning point (T1)) of the first trimming groove (5) to be set as a second turning point (T2). With the second turning point (T2) as a start point, scanning and cutting is performed to forma second trimming groove (6). Thus, the resistance value of the resistor (4) is adjusted to a target resistance value with high precision.

Methods and apparatus providing a vertically constructed, temperature sensing resistor are disclosed. An example apparatus includes a semiconductor substrate including a first doped region, a second doped region, and a third doped region between the first and second doped regions, the third doped region including a temperature sensitive semiconductor material; a first contact coupled to the first doped region; a second contact opposite the first contact coupled to the second doped region; and an isolation trench to circumscribe the third doped region.

A chip component 10 comprises: an insulating substrate 1 on which a resistor 3 serving as a functional element is formed; a pair of internal electrodes (front electrodes 2, end surface electrodes 6, and back electrodes 5) that is formed to cover both end portions of the insulating substrate 1 and connected to the resistor 3; a barrier layer 8 that is formed on a surface of each of the internal electrodes and mainly composed of nickel; and an external connection layer 9 that is formed on a surface of the barrier layer 8 and mainly composed of tin, and the barrier layer 8 is composed of alloy plating (NiP) including nickel and phosphorus, which is formed by electrolytic plating, and a content rate of phosphorus in the alloy plating of an inner region is made different from that of an outer region so that at least the inner region of the barrier layer 8 has magnetic properties.

A chip component 10 comprises: an insulating substrate 1 on which a resistor 3 serving as a functional element is formed; a pair of internal electrodes (front electrodes 2, end surface electrodes 6, and back electrodes 5) that is formed to cover both end portions of the insulating substrate 1 and connected to the resistor 3; a barrier layer 8 that is formed on a surface of each of the internal electrodes and mainly composed of nickel; and an external connection layer 9 that is formed on a surface of the barrier layer 8 and mainly composed of tin, and the barrier layer 8 is composed of alloy plating (NiP) including nickel and phosphorus, which is formed by electrolytic plating, and a content rate of phosphorus in the alloy plating of an inner region is made different from that of an outer region so that at least the inner region of the barrier layer 8 has magnetic properties.