An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.

A core includes a first core part, a second core part, and a spacer. The spacer is between the first core part and the second core part. A board has an opening in which the first core part is inserted, and includes a wiring pattern that wraps around the opening. A magnetic shielding member covers all of the wiring pattern in a plan view of the board, and is insulated from the wiring pattern and the core.

Disclosed herein is a symmetric split planar transformer in the context of a DC-DC isolated converter. The symmetric split planar transformer reduces or eliminates asymmetry in the distribution of parasitic capacitance across the isolation barrier going from one end to another end of a primary coil, and as a result, undesirable electromagnetic interference (EMI) due to common mode dipole emission across the isolation barrier may be reduced. In some embodiments, the primary winding is split into at least a first coil and a second coil, each occupying a different area side-by-side on a substrate. The transformer is symmetric in the sense that a capacitive coupling of the first coil to a secondary winding is the same as a capacitive coupling of the second coil to the secondary winding, such that common mode EMI may be reduced. Each coil may include stacked spiral coil portions in multiple metal planes to increase inductive density across the isolation barrier. Furthermore, in some embodiments the first and second coils may have opposite spiral directions such that far field radiation effect from the transformer may be reduced.

An electronic transformer includes a magnetic core and first and second primary windings formed around the magnetic core. First and second secondary windings are also formed around the magnetic core and are shielded from the first and second primary windings by first and second shield windings. An auxiliary winding provides auxiliary power and is positioned on a same layer as the first shield winding. A compensation winding compensates for current imbalance in the transformer caused by the auxiliary winding and is positioned on a same layer as at least one of the first and the second shield windings.

The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

Devices including a substrate and a plurality of coil portions disposed on the substrate. The plurality of coil portions electrically coupled to form a coil structure.

An electronic component includes an insulating layer, a low voltage conductor pattern formed inside the insulating layer, a high voltage conductor pattern formed inside the insulating layer such as to face the low voltage conductor pattern in an up/down direction, and a withstand voltage enhancement structure of conductive property formed inside the insulating layer and along the high voltage conductor pattern such as to protrude further outside than the low voltage conductor pattern in plan view.

The present description concerns a device comprising at least one chip in a package, the package comprising a support, having the at least one chip resting thereon, and a protection layer covering the at least one chip, the support comprising a stack of layers made of an insulating material, a transformer being formed in the support by first and second conductive tracks.

The following disclosure relates to a planar transformer and a bobbin assembly applied thereto, and more particularly, to a planar transformer in which pins may be firmly fixed through a bobbin body, a bobbin assembly may be conveniently assembled to a transformer board using snap protrusions of the bobbin body, and a total height of the planar transformer may be lowered using a flange part at the time of mounting the planar transformer, and a bobbin assembly applied thereto.

The present invention provides a high efficiency, high density GaN-based power converter comprising: a transformer; a magnetic coupler; a primary switch; a secondary switch; a primary controller; a secondary controller; a multi-layered print circuit board (PCB) comprising: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the transformer, the coupler, a primary switch, a secondary switch, a primary controller and a secondary controller. The power converter further comprises a pair of ferrite cores being fixed to a top surface and a bottom surface of the PCB respectively and commonly shared by the transformer and the coupler.