Patent classifications
H01F41/041
Device Having a Multimode Antenna With Variable Width of Conductive Wire
A method of providing a single structure multiple mode antenna is described. The antenna is preferably constructed having a first inductor coil that is electrically connected in series with a second inductor coil. The antenna is constructed having a plurality of electrical connections positioned along the first and second inductor coils. A plurality of terminals is connected to the electrical connections that facilitate numerous electrical connections and enables the antenna to be selectively tuned to various frequencies and frequency bands.
INDUCTOR AND METHOD FOR PRODUCING THE SAME
The disclosure provides an inductor and a method for producing the same. The inductor includes a first core made of a first magnetic material; at least two windings, configured to be twisted with each other and embedded within the first core, each winding having a pair of terminals extending out of the first core.
MULTILAYER COIL COMPONENT
A multilayer coil component 1 includes an element body 2, a coil 5, a first terminal electrode 3, a second terminal electrode 4, a first connection conductor 6, and a second connection conductor 7. The coil 5 includes a first coil portion 8 that has one end of the coil 5 and is disposed on a side of a main surface 2c and a second coil portion 9 that has the other end of the coil 5 and is disposed on a side of the main surface 2d. A distance L2 between the first connection conductor 6 and the second coil portion 9 is larger than a distance L1 between the first connection conductor 6 and the first coil portion 8.
Systems and methods for an inductor structure having an unconventional turn-ratio in integrated circuits
Embodiments described herein provide circuitry employing one or more inductors having an unconventional turn-ratio. The circuitry includes a primary inductor having a first length located on a first layer of an integrated circuit (IC). The circuitry further includes a secondary inductor having a second length located on a second layer of the IC different from the first layer, whereby the second length is greater than the first length, with a ratio between the first and the second lengths corresponding to a non-integer turn-ratio.
Stacked and interleaved transformer layout
A transformer structure may include a first coil having one or more turns, and a second coil having one or more turns. A turn of the one or more turns of the first coil may overlap a turn of the one or more turns of the second coil in a lateral direction substantially along the turn of the first coil and in a vertical direction substantially along the turn of the first coil. In some implementations, the transformer structure may be integrated in a semiconductor device.
Integrated embedded transformer module
An embedded transformer module device includes an insulating substrate including a first side and a second side opposite to the first side and including a first cavity, a magnetic core in the first cavity, a primary winding wound horizontally around the magnetic core and having a spiral shape with more than one turn, and a secondary winding wound horizontally around the magnetic core, spaced away from the primary winding, and having a spiral shape with more than one turn.
POWER TRANSFORMER OF THE SYMMETRIC-ASYMMETRIC TYPE WITH A FULLY-BALANCED TOPOLOGY
A transformer of the symmetric-asymmetric type includes comprising a primary inductive circuit and a secondary inductive circuit formed in a same plane by respective interleaved and stacked metal tracks. A first crossing region includes a pair of connection plates facing one another, with each connection plate having a rectangular shape that is wider than the metal tracks, and diagonally connected to tracks of the secondary inductive circuit.
STACKED SUBSTRATE INDUCTOR
In conventional device packages, separate standalone inductors are provided and mounted on an interposer substrate along with a die. Separate inductors reduce integration density, decrease flexibility, increase footprint, and generally increase costs. To address such disadvantages, it is proposed to provide a part of an inductor in a substrate below a die. The proposed stacked substrate inductor may include a first inductor in a first substrate, a second inductor in a second a second substrate stacked on the first substrate, and an inductor interconnect coupling the first and second inductors. The core regions of the first and second inductors may overlap with each other at least partially. The proposed stacked substrate inductor may enhance integration density, increase flexibility, decrease footprint, and/or reduce costs.
TWO-DIMENSIONAL STRUCTURE TO FORM AN EMBEDDED THREE-DIMENSIONAL STRUCTURE
Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer. The apparatus further includes a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects.
Package substrate inductor having thermal interconnect structures
Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.