Patent classifications
H01J1/308
Methods for Producing Composite GaN Nanocolumns and Light Emitting Structures Made from the Methods
A method for growing on a substrate strongly aligned uniform cross-section semiconductor composite nanocolumns is disclosed. The method includes: (a) forming faceted pyramidal pits on the substrate surface; (b) initiating nucleation on the facets of the pits; and; (c) promoting the growth of nuclei toward the center of the pits where they coalesce with twinning and grow afterwards together as composite nanocolumns. Multi-quantum-well, core-shell nanocolumn heterostructures can be grown on the sidewalls of the nanocolumns. Furthermore, a continuous semiconductor epitaxial layer can be formed through the overgrowth of the nanocolumns to facilitate fabrication of high-quality planar device structures or for light emitting structures.
NANOPARTICLE-TEMPLATED LITHOGRAPHIC PATTERNING OF NANOSCALE ELECTRONIC COMPONENTS
Some embodiments of vacuum electronics call for nanoscale field-enhancing geometries. Methods and apparatus for using nanoparticles to fabricate nanoscale field-enhancing geometries are described herein. Other embodiments of vacuum electronics call for methods of controlling spacing between a control grid and an electrode on a nano- or micron-scale, and such methods are described herein.
NANOPARTICLE-TEMPLATED LITHOGRAPHIC PATTERNING OF NANOSCALE ELECTRONIC COMPONENTS
Some embodiments of vacuum electronics call for nanoscale field-enhancing geometries. Methods and apparatus for using nanoparticles to fabricate nanoscale field-enhancing geometries are described herein. Other embodiments of vacuum electronics call for methods of controlling spacing between a control grid and an electrode on a nano- or micron-scale, and such methods are described herein.
Nanoparticle-templated lithographic patterning of nanoscale electronic components
Some embodiments of vacuum electronics call for nanoscale field-enhancing geometries. Methods and apparatus for using nanoparticles to fabricate nanoscale field-enhancing geometries are described herein. Other embodiments of vacuum electronics call for methods of controlling spacing between a control grid and an electrode on a nano- or micron-scale, and such methods are described herein.
Nanoparticle-templated lithographic patterning of nanoscale electronic components
Some embodiments of vacuum electronics call for nanoscale field-enhancing geometries. Methods and apparatus for using nanoparticles to fabricate nanoscale field-enhancing geometries are described herein. Other embodiments of vacuum electronics call for methods of controlling spacing between a control grid and an electrode on a nano- or micron-scale, and such methods are described herein.
Microstructured surface with low work function
A horizontal multilayer junction-edge field emitter includes a plurality of vertically-stacked multilayer structures separated by isolation layers. Each multilayer structure is configured to produce a 2-dimensional electron gas at a junction between two layers within the structure. The emitter also includes an exposed surface intersecting the 2-dimensional electron gas of each of the plurality of vertically-stacked multilayer structures to form a plurality of effectively one-dimensional horizontal line sources of electron emission.
Microstructured surface with low work function
A horizontal multilayer junction-edge field emitter includes a plurality of vertically-stacked multilayer structures separated by isolation layers. Each multilayer structure is configured to produce a 2-dimensional electron gas at a junction between two layers within the structure. The emitter also includes an exposed surface intersecting the 2-dimensional electron gas of each of the plurality of vertically-stacked multilayer structures to form a plurality of effectively one-dimensional horizontal line sources of electron emission.
PACKAGE HAVING FIELD EMISSION ELEMENT AND X-RAY DEVICE HAVING THE SAME
A package having a field emission element may include a handle layer; a buried layer stacked on the handle layer; a device layer stacked on the buried layer; an insulating layer stacked in an upper region of the device layer; a gate electrode stacked in an upper region of the insulating layer; and at least one light-emitting element disposed in a lower region of the device layer, and configured to emit light through the device layer. The insulating layer may be configured with a plurality of insulating regions separated by first separation regions, and the gate electrode may be configured with a plurality of metal regions separated by second separation regions. The device layer may be provided with protruding portions disposed to protrude between the first separation regions between the insulating regions and the second separation regions between the metal regions.
ELECTRON SOURCE
According to one embodiment, an electron source includes a first member. The first member includes a first region and a second region. The first region includes In.sub.xAl.sub.yGa.sub.1-x-yN (0x1, 0y1, x+y1). The second region includes diamond including boron.
ELECTRON SOURCE
According to one embodiment, an electron source includes a first member. The first member includes a first region and a second region. The first region includes In.sub.xAl.sub.yGa.sub.1-x-yN (0x1, 0y1, x+y1). The second region includes diamond including boron.