A tunneling electro source, an array thereof and methods for making the same are provided. The tunneling electron source is a surface tunneling micro electron source having a planar multi-region structure. The tunneling electron source includes an insulating substrate, and two conductive regions and one insulating region arranged on a surface of the insulating substrate. The insulating region is arranged between the two conductive regions and abuts on the two conductive regions. Minimum spacing between the two conductive regions, which equals to a minimum width of the insulating region, is less than 100 nm.

A tunneling electro source, an array thereof and methods for making the same are provided. The tunneling electron source is a surface tunneling micro electron source having a planar multi-region structure. The tunneling electron source includes an insulating substrate, and two conductive regions and one insulating region arranged on a surface of the insulating substrate. The insulating region is arranged between the two conductive regions and abuts on the two conductive regions. Minimum spacing between the two conductive regions, which equals to a minimum width of the insulating region, is less than 100 nm.

A tunneling electro source, an array thereof and methods for making the same are provided. The tunneling electron source is a surface tunneling micro electron source having a planar multi-region structure. The tunneling electron source includes an insulating substrate, and two conductive regions and one insulating region arranged on a surface of the insulating substrate. The insulating region is arranged between the two conductive regions and abuts on the two conductive regions. Minimum spacing between the two conductive regions, which equals to a minimum width of the insulating region, is less than 100 nm.

In an embodiment, a method includes forming a first diamond layer on a substrate and inducing a layer of graphene from the first diamond layer by heating the substrate and the first diamond layer. The method includes forming a second diamond layer on top of the layer of graphene and applying a mask to the second diamond layer. The mask includes a shape of a cathode, an anode, and one or more grids. The method further includes forming a two-dimensional cold cathode, a two-dimensional anode, and one or more two-dimensional grids by reactive-ion electron-beam etching. Each of the two-dimensional cold cathode, the two-dimensional anode, and the one or more two-dimensional grids includes a portion of the first diamond layer, the graphene layer, and the second diamond layer such that the graphene layer is positioned between the first diamond layer and the second diamond layer.

A laminated body is provided in a circumferential shape with a gap formed in a part of a circumferential direction on a semiconductor layer. In the laminated body, a first insulating layer, a gate layer, a second insulating layer, and a drain layer are layered in this order from the semiconductor layer side. An impurity diffusion layer is formed on a surface of the semiconductor layer, and a backside electrode on a backside surface. The impurity diffusion layer extends from a position in contact with side walls in a channel space to an outside of the laminated body through a region corresponding to the gap on the surface of the semiconductor layer. A portion of the impurity diffusion layer beyond the laminated body is a contact region to which a wiring for applying a predetermined voltage is connected. A cover layer made of an insulating material is formed in an upper portion and a periphery of the annular portion including the laminated body and the gap.