Disclosed embodiments apply electron beams to substrates for microelectronic workpieces to improve plasma etch and deposition processes. The electron beams are generated and directed to substrate surfaces using DC (direct current) biasing, RF (radio frequency) plasma sources, and/or other electron beam generation and control techniques. For certain embodiments, DC-biased RF plasma sources, such as DC superposition (DCS) or hybrid DC-RF sources, are used to provide controllable electron beams on surfaces opposite a DC-biased electrode. For certain further embodiments, the DC-biased electrode is pulsed. Further, electron beams can also be generated through electron beam extraction from external and/or non-ambipolar sources. The disclosed techniques can also be used with additional electron beam sources and/or additional etch or deposition processes.

A method for processing a semiconductor substrate is described herein. The method described herein includes generating fluorine radicals and ions, delivering the fluorine radicals through an ion blocker to a processing region, and removing one or more portions of a gate structure to expose one or more portions of a gate dielectric material disposed thereunder. The gate structure includes at least two ceramic or metal layers, and the gate dielectric material is made of a high-k dielectric material. A substrate having the gate structure and gate dielectric material formed thereon is disposed in the processing region, and the temperature of the substrate is maintained at about 60 degrees Celsius or higher. By etching the gate structure using fluorine radicals at a temperature greater or equal to 60 degrees Celsius, the at least two ceramic or metal layers have a flat cross sectional profile.

Methods of decreasing the dose per pulse implanted into a workpiece disposed in a process chamber are disclosed. According to one embodiment, the plasma is generated by a RF power supply. This RF power supply may have two different modes, a first, referred to as continuous wave mode, where the RF power supply is continuously outputting a voltage. This mode allows creation of the plasma within the process chamber. During the second mode, referred to as pulsed plasma mode, the RF power supply outputs two different power levels. The platen bias voltage may be a more negative value when the lower RF power level is being applied. This pulsed (or multi-setpoint) plasma also assists in reducing dopant deposition on the wafer during the time when CW plasma is on but the bias voltage pulse is in the off-state. In a further embodiment, a delay is introduced between the transition to the pulsed plasma mode and the initiation of the implanting process. In yet another embodiment the plasma is generated at a location in the chamber more judicious to reducing the dose impinging on the wafer, thereby increasing the process time to allow adequate control of the process.

Disclosed is a plasma processing method including: growing a polycrystalline silicon layer on a processing target base body; and exposing the polycrystalline silicon layer to hydrogen radicals by supplying a processing gas containing hydrogen into a processing container that accommodates the processing target base body including the polycrystalline silicon layer grown thereon and radiating microwaves within the processing container to generate the hydrogen radicals.

A virtual cathode deposition apparatus utilises virtual plasma cathode for generation of high density electron beam to ablate a solid target. A high voltage electrical pulse ionizes gas to produce a plasma which temporarily appears in front of the target and serves as the virtual plasma cathode at the vicinity of target. This plasma then disappears allowing the ablated target material in a form of a plasma plume to propagate toward the substrate. Several virtual cathodes operating in parallel provide plumes that merge into a uniform plasma which when condensing on a nearby substrate leads to wide area deposition of a uniform thickness thin film.

The embodiments herein relate to methods and apparatus for etching features in semiconductor substrates. In a number of cases, the features may be etched while forming a spin-torque-transfer random access memory (STT-RAM) device. In various embodiments, the substrate may be cooled to a low temperature via a cooled substrate support during particular processing steps. The cooled substrate support may have beneficial impacts in terms of reducing the degree of diffusion-related damage in a resulting device. Further, the use of a non-cooled substrate support during certain other processing steps can likewise have beneficial impacts in terms of reducing diffusion-related damage, depending on the particular step. In some implementations, the cooled substrate support may be used in a process to preferentially deposit a material (in some cases a reactant) on certain portions of the substrate. The disclosed embodiments may be used to achieve high quality anisotropic etching results.

There is disclosed a substrate processing method for etching a substrate on which a first and a second silicon oxide layer having different film qualities are formed side by side. The substrate processing method includes: a first etching step of supplying a halogen-containing gas that is not activated to the substrate and sublimating reaction by-products generated by reaction between the halogen-containing gas and the first and the second silicon oxide layer; and a second etching step of etching the substrate by radicals generated by activating the halogen-containing gas.

An ion implantation system having a grid assembly. The system includes a plasma source configured to provide plasma in a plasma region; a first grid plate having a plurality of apertures configured to allow ions from the plasma region to pass therethrough, wherein the first grid plate is configured to be biased by a power supply; a second grid plate having a plurality of apertures configured to allow the ions to pass therethrough subsequent to the ions passing through the first grid plate, wherein the second grid plate is configured to be biased by a power supply; and a substrate holder configured to support a substrate in a position where the substrate is implanted with the ions subsequent to the ions passing through the second grid plate.

A gas blocking layer forming apparatus comprises a vacuum chamber that provides a space where a chemical vapor deposition process and a sputtering process are performed; a holding unit that is provided at a lower side within the vacuum chamber and mounts thereon a target object on which an organic/inorganic mixed multilayer gas blocking layer is formed; a neutral particle generation unit that is provided at an upper side within the vacuum chamber and generates a neutral particle beam having a high-density flux with a current density of about 10 A/m.sup.2 or more; and common sputtering devices that are provided at both sides of the neutral particle generation unit, wherein each common sputtering device has a sputtering target of which a surface is inclined toward a surface of the target object.

A film thickness distribution exists in a substrate plane after CMP step. This film thickness distribution results in, for example, variation in gate threshold value voltages of metal gates, and causes variation in element characteristics. It is an object of the present invention to easily improve the film thickness distribution processed by this CMP step. By using the ion beam etching method after the CMP step, the film thickness distribution in the plane of the substrate 111 is corrected. More specifically, when the ion beam etching is performed, the plasma density in the plasma generation chamber 102 is caused to be different between a position facing a central portion in the plane of the substrate 111 and a position facing an outer peripheral portion, so that the etching rate in the central portion in the plane of the substrate 111 and the etching rate in the outer peripheral portion in the substrate plane 111 are caused to be different.