A plasma generator is described comprising an elongate member having a distal end, a proximal end, and a lumen extending therethrough, the proximal end configured to be connectable to a source of an inert gas, a plasma generation tip disposed at the distal end of the elongate member, the plasma generation tip configured to be in electrical communication with a power source, and an activation switch configured to control generation of plasma at the plasma generation tip, wherein the plasma generator is configured to be operably connectable to a medical device.

Provided herein are methods and apparatuses for controlling uniformity of processing at an edge region of a semiconductor wafer. In some embodiments, the methods include exposing an edge region to treatment gases such as etch gases and/or inhibition gases. Also provided herein are exclusion ring assemblies including multiple rings that may be implemented to provide control of the processing environment at the edge of the wafer.

A reactive particles supply system that may include an adjustable gas supply unit that is arranged to supply gas and to set a gas condition, a reactive particles supply unit that may be arranged to receive the gas, and an adjustable reactive particles output unit that may include a reactive particles input, a second reactive particles output, and a reactive particles path. The second reactive particles output is configured to output reactive particles towards an opening of a vacuumed chamber. The adjustable reactive particles output unit is arranged to mechanically configure at least one element of the reactive particles path according to the reactive particles condition.

Exemplary semiconductor processing chambers include a chamber body defining a processing region. The chambers may include a substrate support disposed within the processing region. The substrate support may have an upper surface that defines a recessed substrate seat. The chambers may include a shadow ring disposed above the substrate seat and the upper surface. The shadow ring may extend about a peripheral edge of the substrate seat. The chambers may include bevel purge openings defined within the substrate support proximate the peripheral edge. A bottom surface of the shadow ring may be spaced apart from a top surface of the upper surface to form a purge gas flow path that extends from the bevel purge openings along the shadow ring. A space formed between the shadow ring and the substrate seat may define a process gas flow path. The gas flow paths may be in fluid communication with one another.

A linear processing system having an entry loadlock, a first multi-pass processing chamber coupled to the entry loadlock, the first multi-pass processing chamber having a sputtering magnetron arrangement and configured to house a single substrate carrier for performing a multi-pass processing; a single-pass chamber coupled to the first multi-pass processing chamber and having a plurality of magnetron arrangements arranged along a carrier travel direction, the single-pass chamber configured to house multiple carriers arranged serially in a row and configured for a single-pass processing; a second multi-pass processing chamber coupled to the single-pass processing chamber, the second multi-pass processing chamber having a sputtering magnetron arrangement and configured to house a single substrate carrier for performing a multi-pass processing; and an exit loadlock chamber coupled to the second multi-pass processing chamber.

In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.

A method of post-deposition treatment for silicon oxide film includes: providing in a reaction space a substrate having a recess pattern on which a silicon oxide film is deposited; supplying a reforming gas for reforming the silicon oxide film to the reaction space in the absence of a film-forming precursor, said reforming gas being composed primarily of He and/or H.sub.2; and irradiating the reforming gas with microwaves in the reaction space having a pressure of 200 Pa or less to generate a direct microwave plasma to which the substrate is exposed, thereby reforming the silicon oxide film.

A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

A method of plasma etching a semiconductor wafer includes: securing the semiconductor wafer to a mounting platform within a process chamber such that an outer edge of the semiconductor wafer is encircled by a sloped annular ring having a plurality of perforation therein, the sloped annular ring having an inner edge at a first end of the sloped annular ring and an outer edge at a second end of the sloped annular ring. Suitably, the first end is opposite the second end and the first end resides in a first plane and the second end resides in a second plane different from the first plane. The method further includes generating a plasma within the process chamber such that the semiconductor wafer is exposed to the plasma and creating a flow of at least one of plasma and gas through the perforations in the sloped annular ring.

A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.