It would be helpful to provide a wafer separation apparatus and method, and a method for manufacturing a silicon wafer in which poor wafer separation can be easily prevented. A wafer separation apparatus 1 includes an injection port 2 configured to inject a fluid, a rolling element 3, and a holder 4 configured to movably hold the rolling element 3 in a rollable and integral manner, to be reciprocatable and biased to one side in a reciprocating direction, and to be integrally connected to the injection port 2.

Methods and apparatus for processing a substrate include cleaning and self-assembly monolayer (SAM) formation for subsequent reverse selective atomic layer deposition. An apparatus may include a process chamber with a processing volume and a substrate support including a pedestal, a remote plasma source fluidly coupled to the process chamber and configured to produce radicals or ionized gas mixture with radicals that flow into the processing volume to remove residue or oxides from a surface of the substrate, a first gas delivery system with a first ampoule configured to provide at least one first chemical into the processing volume to produce a SAM on the surface of the substrate, a heating system located in the pedestal and configured to heat a substrate by flowing gas on a backside of the substrate, and a vacuum system fluidly coupled to the process chamber and configured to control heating of the substrate.

A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.

A method includes receiving a carrier with a plurality of wafers inside; supplying a purge gas to an inlet of the carrier; extracting an exhaust gas from an outlet of the carrier; and generating a health indicator of the carrier while performing the supplying of the purge gas and the extracting of the exhaust gas.

Semiconductor devices and fin field effect transistors (FinFETs) are disclosed. In some embodiments, a representative semiconductor device includes a group III material over a substrate, the group III material comprising a thickness of about 2 monolayers or less, and a group III-V material over the group III material.

A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.

A method for etching a main surface of a thin layer of a substrate, which comprises immersing the substrate in an etching bath so as to expose the main surface to an etching agent, the substrate being oriented relative to the bath such that:when it is introduced into the bath, the main surface is gradually immersed from an initial introduction point (PII) to an end introduction point (PFI), at an introduction speed, andwhen it exits the bath, the main surface gradually emerges from an initial exit point (PIS) to an end exit point (PFS), at an exit speed, the method being characterized in that:the introduction speed is chosen in such a way as to etch the main surface according to a first non-uniform profile between the initial introduction point (PII) and the end introduction point (PFI), and/orthe exit speed is chosen in such a way as to etch the main surface according to a second non-uniform profile between the initial exit point (PIS) and the end exit point (PFS), in order to compensate for non-uniformities in the thickness of the thin layer.

During a pre-treat process, hydrogen plasma is used to remove contaminants (e.g., oxygen, carbon) from a surface of a wafer. The hydrogen plasma may be injected into the plasma chamber via an elongated injector nozzle. Using such elongated injector nozzle, a flow of hydrogen plasma with a significant radial velocity flows over the wafer surface, and transports volatile compounds and other contaminant away from the wafer surface to an exhaust manifold. A protective liner made from crystalline silicon or polysilicon may be disposed on an inner surface of the plasma chamber to prevent contaminants from being released from the surface of the plasma chamber. To further decrease the sources of contaminants, an exhaust restrictor made from silicon may be employed to prevent hydrogen plasma from flowing into the exhaust manifold and prevent volatile compounds and other contaminants from flowing from the exhaust manifold back into the plasma chamber.

A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.

A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.