H01L21/02043

Shutter disk

Describes are shutter disks comprising one or more of titanium (Ti), barium (Ba), or cerium (Ce) for physical vapor deposition (PVD) that allows pasting to minimize outgassing and control defects during etching of a substrate. The shutter disks incorporate getter materials that are highly selective to reactive gas molecules, including O.sub.2, CO, CO.sub.2, and water.

STACKED WAFER STRUCTURE AND METHOD FOR FORMING THE SAME

A method includes bonding a front side surface of a first wafer to a front side of a second wafer; forming a bonding material on a periphery of the first wafer and a periphery of the second wafer; performing a thinning process on the first wafer from a back side surface of the first wafer; after performing the thinning process, performing a trimming process from the back side surface of the first wafer to remove a first portion of the bonding material and partially trim down the periphery of the second wafer from a front side surface of the second wafer.

APPARATUS AND METHOD OF TREATING SURFACE OF SEMICONDUCTOR SUBSTRATE

In one embodiment, an apparatus of treating a surface of a semiconductor substrate comprises a substrate holding and rotating unit, first to fourth supplying units, and a removing unit. A substrate holding and rotating unit holds a semiconductor substrate, having a convex pattern formed on its surface, and rotates the semiconductor substrate. A first supplying unit supplies a chemical onto the surface of the semiconductor substrate in order to clean the semiconductor substrate. A second supplying unit supplies pure water to the surface of the semiconductor substrate in order to rinse the semiconductor substrate. A third supplying unit supplies a water repellent agent to the surface of the semiconductor substrate in order to form a water repellent protective film onto the surface of the convex pattern. A fourth supplying unit supplies alcohol, which is diluted with pure water, or acid water to the surface of the semiconductor substrate in order to rinse the semiconductor substrate. A removing unit removes the water repellent protective film with the convex pattern being left.

Method for pretreatment of base substrate and method for manufacturing layered body using pretreated base substrate

Provided is a method for pretreatment of a group III nitride single crystal substrate having a high Al composition ratio, for manufacturing a high-quality group III nitride thin film. The method includes heating the base substrate at a temperature range of 1000 to 1250 C. for no less than 5 minutes under a first mixed gas atmosphere before a layer of a second group III nitride single crystal is grown, wherein the first mixed gas includes hydrogen gas and nitrogen gas; the base substrate includes a layer of a first group III nitride single crystal at least on a surface of the base substrate; the first group III nitride single crystal is represented by a composition formula of Al.sub.AGa.sub.BIn.sub.CN; and the layer of the second group III nitride single crystal is to be grown on the layer of the first group III nitride single crystal.

BINARY METAL OXIDE BASED INTERLAYER FOR HIGH MOBILITY CHANNELS
20180040708 · 2018-02-08 ·

A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.

BINARY METAL OXIDE BASED INTERLAYER FOR HIGH MOBILITY CHANNELS
20180040709 · 2018-02-08 ·

A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.

BINARY METAL OXIDE BASED INTERLAYER FOR HIGH MOBILITY CHANNELS
20180040710 · 2018-02-08 ·

A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.

Systems and Methods for Treating Substrates with Cryogenic Fluid Mixtures
20180025904 · 2018-01-25 ·

Disclosed herein are systems and methods for treating the surface of a microelectronic substrate, and in particular, relate to an apparatus and method for scanning the microelectronic substrate through a cryogenic fluid mixture used to treat an exposed surface of the microelectronic substrate. The fluid mixture may be expanded through a nozzle to form an aerosol spray or gas cluster jet (GCJ) spray may impinge the microelectronic substrate and remove particles from the microelectronic substrate's surface. In one embodiment, the process conditions may be varied between subsequent treatments of a single substrate to target different types of particles with each treatment.

Post-CMP cleaning and apparatus

A method includes performing a first post Chemical Mechanical Polish (CMP) cleaning on a wafer using a first brush. The first brush rotates to clean the wafer. The method further includes performing a second post-CMP cleaning on the wafer using a second brush. The second brush rotates to clean the wafer. The first post-CMP cleaning and the second post-CMP cleaning are performed simultaneously.

System with substrate carrier deterioration detection and repair

A system includes a plurality of semiconductor processing tools; a carrier purge station; a carrier repair station; and an overhead transport (OHT) loop for transporting one or more substrate carriers among the plurality of semiconductor processing tools, the carrier purge station, and the carrier repair station. The carrier purge station is configured to receive a substrate carrier from one of the plurality of semiconductor processing tools, purge the substrate carrier with an inert gas, and determine if the substrate carrier needs repair. The carrier repair station is configured to receive a substrate carrier to be repaired and replace one or more parts in the substrate carrier.