Patent classifications
H01L21/02076
Temporary bonding scheme
A method includes filling a trench formed in a first integrated circuit carrier with temporary bonding material to form a temporary bonding layer. At least one chip is bonded over the temporary bonding layer.
Protective film agent for laser dicing
A protective film agent for laser dicing that includes a solution in which at least a water-soluble resin, an organic solvent, and an ultraviolet absorber are mixed and in which the content of sodium (Na) of the solution is equal to or lower than 100 ppb in weight ratio. Preferably, the solution further includes an antioxidant.
WAFER PROCESSING METHOD
A wafer processing method includes forming a start point of division along division lines, providing, on a front surface of the wafer, a protective member for protecting the front surface of the wafer, grinding a back surface of the wafer to a desired thickness, forming division grooves in the division lines to divide the wafer into individual device chips, providing an expandable sheet to the back surface of the wafer and removing the protective member from the front surface of the wafer, coating the front surface of the wafer with an adhesive liquid having flowability, expanding and shrinking the sheet so as to allow the adhesive liquid to enter each of the division grooves and to discharge the adhesive liquid from the division grooves, and removing the adhesive liquid from the front surface of the wafer to clean a side surface of each of the division grooves.
SEMICONDUCTOR DEVICE AND CHIP SINGULATION METHOD
A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 μm; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 μm. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-μm square region located at least 13 μm inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.
Workpiece processing method
A processing method for a workpiece includes a cutting step of cutting the workpiece along streets by a cutting blade having a V-shaped tip end, to form V grooves of which shallower parts are wider than deeper parts, and a cleaning step of cleaning a back surface of the workpiece with cleaning water, after the cutting step is carried out.
Method of reducing residual contamination in singulated semiconductor die
A method for processing electronic die includes providing a substrate having a plurality of electronic die formed as part of the substrate and separated from each other by spaces. The method includes placing the substrate onto a first carrier substrate. The method includes plasma etching the substrate through the spaces to form singulation lines adjacent the plurality of electronic die. The method includes exposing the plurality of electronic die to solvent vapors, such as heated solvent vapors, under reduced pressure to reduce the presence of residual contaminants resulting from the plasma etching step.
Disposing protective cover film and underfill layer over singulated integrated circuit dice for protection during integrated circuit processing
Singulated integrated circuit (IC) dice are provided. The singulated IC dice are positioned on dicing tape to provide open space between sides of adjacent singulated IC dice. An underfill layer and a protective cover film is disposed above the singulated IC dice and the open space between the sides of the adjacent singulated IC dice. The underfill layer and the protective cover film include one or more photodefinable materials. An exposure operation is performed to produce a pattern on the underfill layer and the protective cover film. Based on the pattern, the underfill layer and the protective cover film is removed at areas above the open space between the sides of the adjacent singulated IC dice to create portions of the underfill layer and portions of the protective cover film that are disposed above the singulated IC dice.
PROCESSED STACKED DIES
Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.
CHIP BONDING METHOD
A die bonding method is disclosed, through coating bonding adhesive on front side of device wafer and bonding carrier wafer thereto, back-side connection structure can be formed on back side of device wafer to lead out an interconnect structure in device wafer to back side of device wafer, and dies thereon can be bonded at front sides to target wafer. Moreover, after device wafer is debonded from carrier wafer, the bonding adhesive is retained on front side of device wafer to provide protection to front side of device wafer during subsequent dicing of device wafer, and to avoid particles or etching by-products produced during dicing process from adhering to front side of device wafer. Such etching by-products are subsequently removed along with the bonding adhesive, ensuring cleanness of front sides of individual dies resulting from dicing process and improved quality of bonding of dies at front sides to target wafer.
WAFER CLEANING WITH WAFER ASSEMBLY PRESENCE DETECTION
A system for cleaning a wafer has a vacuum source, a chuck table configured to support a wafer assembly and to be in communication with both the vacuum source and the wafer assembly, such that in use a suction force is applied to the wafer assembly via the chuck table. The system also includes a sensor component configured to detect the presence of the wafer assembly on the chuck table.