A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.

A method of in-situ transfer during fabrication of a component comprising a 2-dimensional crystalline thin film on a substrate is disclosed. In one embodiment, the method includes forming a layered structure comprising a polymer, a 2-dimensional crystalline thin film, a metal catalyst, and a substrate. The metal catalyst, being a growth medium for the two-dimensional crystalline thin film, is etched and removed by infiltrating liquid to enable the in-situ transfer of the two-dimensional crystalline thin film directly onto the underlying substrate.

A method for producing a GaN crystal that includes: (i) a seed crystal preparation step of preparing a GaN seed crystal having one or more facets selected from a {10-10} facet and a {10-1-1} facet; and (ii) a growth step of growing GaN from vapor phase on a surface comprising the one or more facets of the GaN seed crystal using GaCl.sub.3 and NH.sub.3 as raw materials.

A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.

A semiconductor device with favorable reliability is provided. The semiconductor device includes a first insulator; a second insulator positioned over the first insulator; an oxide positioned over the second insulator; a first conductor and a second conductor positioned apart from each other over the oxide; a third insulator positioned over the oxide, the first conductor, and the second conductor; a third conductor positioned over the third insulator and at least partly overlapping with a region between the first conductor and the second conductor; a fourth insulator positioned to cover the oxide, the first conductor, the second conductor, the third insulator, and the third conductor; a fifth insulator positioned over the fourth insulator; and a sixth insulator positioned over the fifth insulator. An opening reaching the second insulator is formed in at least part of the fourth insulator; the fifth insulator is in contact with the second insulator through the opening; and the first insulator, the fourth insulator, and the sixth insulator have a lower oxygen permeability than the second insulator.

Selective deposition methods are described. An exemplary method comprises exposing the substrate comprising a first surface and a second surface to an anchor reactant and selectively depositing the anchor reactant on the first surface as a seed layer, wherein the anchor reactant comprises an ethynyl derivative with a headgroup that selectively targets the first surface.

A silicon carbide semiconductor device includes a semiconductor element with a MOS structure having: a substrate; a drift layer on the substrate; a base region on the drift layer; a source region on the base region; a trench gate structure having a gate insulation film and a gate electrode in a gate trench disposed from a surface of the source region to be deeper than the base region; an interlayer insulation film covering the gate electrode and the gate insulation film; a source electrode on the interlayer insulation film, the source region and the base region; and a drain electrode. The semiconductor element flows a current when a gate voltage is applied to the gate electrode and a channel region is provided in a portion of the base region in contact with the trench gate structure.

A silicon layer etchant composition and associated methods, the composition including about 1 wt % to about 20 wt % of an alkylammonium hydroxide; about 1 wt % to about 30 wt % of an amine compound; about 0.01 wt % to about 0.2 wt % of a nonionic surfactant including both a hydrophobic group and a hydrophilic group; and water, all wt % being based on a total weight of the silicon layer etchant composition.

Provided is a semiconductor element including at least, a semiconductor layer including a crystalline oxide semiconductor as a major component; an electrode layer laminated on the semiconductor layer; and a conductive substrate laminated on the electrode layer directly or with another layer in between, the conductive substrate containing at least a first metal selected from the metals in group 11 in the periodic table and a second metal different from the first metal in coefficient of liner thermal expansion.

A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.