Provided is a substrate holder where an effect of a pressure of a plating solution can be suppressed. A substrate holder includes first and second holding members for sandwiching a substrate. The first holding member includes: a support base; a movable base for supporting the substrate; and a biasing mechanism disposed between the support base and the movable base, and biasing the movable base in a direction along which the movable base is separated from the support base. The second holding member includes a protruding portion brought into contact with the substrate so as to seal the substrate. A biasing force of the biasing mechanism which is applied to a region or a position of the movable base differs from a biasing force of the biasing mechanism which is applied to another region or at another position of the movable base.

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a jog; a jog; and jog; a jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.

A light emitting device includes a substrate, an adhesion layer, a micro light emitting device (LED), a first conductive layer, and a second conductive layer. A light emitting surface of the LED is away from the substrate. The LED includes a first semiconductive layer, a second semiconductive layer, a tether layer, a first electrode, and a second electrode. The tether layer covers a portion of sidewalls of the first semi-conductive layer, a portion of a bottom surface of the first semi-conductive layer, sidewalls of the second semiconductive layer, and a portion of a bottom surface of the second semiconductive layer. The first electrode and the second electrode are respectively electrically connected to the first semiconductive layer and the second semiconductive layer. The first conductive layer and the second conductive layer are respectively electrically connected to the first electrode and the second electrode.

A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.

A method for producing an organic electronic device is disclosed. In an embodiment the method includes applying an organic material to a substrate to form at least one organic functional layer, applying a patterned electrode material to the at least one organic functional layer by a first mask, and removing the organic material from regions which are free of the electrode material.

Disclosed are methods and systems for depositing layers comprising vanadium, nitrogen, and element selected from the list consisting of molybdenum, tantalum, niobium, aluminum, and silicon. The layers are deposited onto a surface of a substrate. The deposition process may be a cyclical deposition process. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, metal-insulator-metal (MIM) structures, and DRAM capacitors.

An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a jog; a jog; an jog; a jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.

Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.

Metal chemical vapor deposition approaches for fabricating wrap-around contacts, and semiconductor structures having wrap-around metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor feature above a substrate. A dielectric layer is over the semiconductor feature, the dielectric layer having a trench exposing a portion of the semiconductor feature, the portion having a non-flat topography. A metallic contact material is directly on the portion of the semiconductor feature. The metallic contact material is conformal with the non-flat topography of the portion of the semiconductor feature. The metallic contact material has a total atomic composition including 95% or greater of a single metal species.