A heat treatment apparatus is provided which includes heating means for enabling a rapid temperature rise to a temperature of 1600 through 1900° C., and a thermometer capable of accurately measuring temperatures even when rapid temperature rises and drops are repeated, the heat treatment apparatus being capable of performing heat treatment of an SiC substrate with good mass productivity after ion implantation. The heat treatment apparatus enables the heat treatment of a semiconductor substrate at 1600 to 1900° C. by temperature control using a resistance heating element and thermocouple thermometers. The heat treatment apparatus is configured such that the resistance heating element and the thermocouple thermometers include a common constituent metal as a main component.

A method of cleaning a wafer comprises: a scrubbing operation comprising treating a target wafer to be cleaned with a brush at a rotation rate of 200 rpm or less to prepare a brush cleaned wafer; and a cleaning operation comprising cleaning the brush cleaned wafer with a cleaning solution to prepare a cleaned bare wafer, wherein the cleaning operation comprises a first cleaning operation and a second cleaning operation sequentially.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

A method of forming a semiconductor structure, the method comprises: providing a non-planar surface in the manufacturing of a silicon carbide (SiC) device; depositing a reflowable dielectric material on said non-planar surface; and heating said reflowable dielectric material to a temperature and for a time sufficient to cause reflowing of said reflowable dielectric material and thereby provide a dielectric layer comprising a substantially planar surface, wherein said dielectric layer is substantially free of voids.

A method for manufacturing a semiconductor device having a junction field effect transistor, includes: preparing a substrate having a first conductivity type drift layer; forming a first conductivity type channel layer above the drift layer by an epitaxial growth, to thereby produce a semiconductor substrate; forming a second conductivity type gate layer within the channel layer by performing an ion-implantation; forming a second conductivity type body layer at a position separated from the gate layer within the channel layer by performing an ion-implantation; and forming a second conductivity type shield layer at a position that is to be located between the gate layer and the drift layer within the channel layer by performing an ion-implantation. The shield layer is formed to face the gate layer while being separated from the gate layer, and is kept to a potential different from that of the gate layer.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

A method includes providing a layer of porous silicon carbide supported by a silicon carbide substrate, providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide, forming a plurality of semiconductor devices in the layer of epitaxial silicon carbide, and separating the substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. Additional methods are described.

A method of splitting a semiconductor wafer includes: forming one or more epitaxial layers on the semiconductor wafer; forming a plurality of device structures in the one or more epitaxial layers; forming a metallization layer and/or a passivation layer over the plurality of device structures; attaching a carrier to the semiconductor wafer with the one or more epitaxial layers, the carrier protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; forming a separation region within the semiconductor wafer, the separation region having at least one altered physical property which increases thermo-mechanical stress within the separation region relative to the remainder of the semiconductor wafer; and applying an external force to the semiconductor wafer such that at least one crack propagates along the separation region and the semiconductor wafer splits into two separate pieces, one of the pieces retaining the plurality of device structures.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

A SiC wafer including a SiC substrate and an epitaxial layer formed on the SiC substrate and containing SiC is provided, and a composition ratio of C—Si of an upper surface of the epitaxial layer is 50 atm % or less.