A method of manufacturing and using micro assembler systems are described. A method of manufacturing includes disposing a first plurality of electrodes above a first zone of the substrate, wherein the first plurality of electrodes has a first range of spacing. The method further includes disposing a second plurality of electrodes above a second zone of the substrate, wherein the second plurality of electrodes has a second range of spacing that is less than the first range of spacing. A method of using micro assembler systems includes disposing a mobile particle at least partially submersed in an assembly medium above a substrate, a first plurality of electrodes and a second plurality of electrodes. The method further includes conducting a field through individual electrodes of the first plurality of electrodes and the second plurality of electrodes to generate electrophoretic forces or dielectrophoretic forces on the mobile particle.

A method of manufacturing and using micro assembler systems are described. A method of manufacturing includes disposing a first plurality of electrodes above a first zone of the substrate, wherein the first plurality of electrodes has a first range of spacing. The method further includes disposing a second plurality of electrodes above a second zone of the substrate, wherein the second plurality of electrodes has a second range of spacing that is less than the first range of spacing. A method of using micro assembler systems includes disposing a mobile particle at least partially submersed in an assembly medium above a substrate, a first plurality of electrodes and a second plurality of electrodes. The method further includes conducting a field through individual electrodes of the first plurality of electrodes and the second plurality of electrodes to generate electrophoretic forces or dielectrophoretic forces on the mobile particle.

Implementations of image sensors may include a first die including an image sensor array and a first plurality of interconnects where the image sensor array includes a plurality of photodiodes and a plurality of transfer gates. The image sensor array may also include a second die including a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors. The first die may be coupled to the second die through the first plurality of interconnects and through the second plurality of interconnects. No more than eight photodiodes of the plurality of photodiodes of the first die may be electrically coupled with no more than four capacitors of the plurality of capacitors.

A device for heating a substrate according to a predetermined temperature profile for crystallizing a material on the substrate includes: a housing, at least a process chamber situated inside the housing and provided with a first and second opening for passing through a substrate, an inlet for introducing a process gas which includes the material in vapor phase into the chamber, at least two transport rollers attached to the housing for transporting the substrate into the chamber. The device further includes passage spaces for preventing the escape of process gas from the chamber to a space between the chamber and housing, which are situated near respective ends of the transport rollers in the chamber, the respective passage spaces having a first passage opening on an inner wall of the chamber, a second passage opening on an outer wall of the chamber and a first flange fixed around the transport roller.

A device for heating a substrate according to a predetermined temperature profile for crystallizing a material on the substrate includes: a housing, at least a process chamber situated inside the housing and provided with a first and second opening for passing through a substrate, an inlet for introducing a process gas which includes the material in vapor phase into the chamber, at least two transport rollers attached to the housing for transporting the substrate into the chamber. The device further includes passage spaces for preventing the escape of process gas from the chamber to a space between the chamber and housing, which are situated near respective ends of the transport rollers in the chamber, the respective passage spaces having a first passage opening on an inner wall of the chamber, a second passage opening on an outer wall of the chamber and a first flange fixed around the transport roller.

A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

A substrate processing method comprises: a liquid film forming step of forming a liquid film of a rinsing liquid on a pattern forming surface of a substrate formed with a pattern; a liquid pool forming step of forming a liquid pool of an organic solvent by supplying the organic solvent to the liquid film near a center of rotation of the substrate; a replacement step of replacing the rinsing liquid constituting the liquid film with the organic solvent by supplying the organic solvent to the liquid pool while rotating the substrate at a rotational speed higher than in the liquid pool forming step; an application step of applying a filler solution to the pattern forming surface coated with the organic solvent; and a filling step of causing a filler contained in the filler solution and applied to the pattern forming surface to sink and filling concave portions of the pattern with the filler.

A substrate processing apparatus according to the present disclosure includes a holding unit, a nozzle, a driving unit, and a controller. The holding unit holds a substrate. The nozzle supplies a processing liquid to the substrate held on the holding unit. The driving unit moves the nozzle. The controller controls the driving unit, so as to move the nozzle while supplying the processing liquid to the substrate from the nozzle. Further, the controller controls the driving unit based on recipe information including step information including positions of first and second points above the substrate, total time for moving the nozzle between the first and second points, and a moving speed of the nozzle, so as to cause reciprocation of the nozzle.

Multi-qubit devices and quantum computers including the same are provided. The multi-qubit device may include a first layer including a plurality of qubits; a second layer that is disposed on the first layer, and comprises a plurality of flux generating elements that apply flux to the plurality of qubits, a plurality of wire patterns that provide current to the plurality of flux generating elements, and a plurality of plugs that are disposed perpendicular to the plurality of flux generating elements and the plurality of wire patterns and interconnect the plurality of flux generating elements and the plurality of wire patterns. Each of the plurality of flux generating elements may be integrated with a corresponding one of the plurality of wire patterns and a corresponding one of the plurality of plugs.