A target made of a metal material is sputtered to form a metal film on a silicon carbide wafer. At this time, the metal film is formed under a condition that an incident energy of incidence, on the silicon carbide wafer, of the metal material sputtered from the target and a sputtering gas flowed in through a gas inlet port is lower than a binding energy of silicon carbide, and more specifically lower than 4.8 eV. For example, the metal film is formed while a high-frequency voltage applied between a cathode and an anode is set to be equal to or higher than 20V and equal to or lower than 300V.

A method for producing a resistive random access memory includes preparing a first metal layer and sputtering a resistive switching layer on the first metal layer. Surface treatment is conducted on the resistive switching layer by using a plasma containing mobile ions to dope the mobile ions into the resistive switching layer. The polarity of the mobile ions is opposite to the polarity of oxygen ions. Then, a second metal layer is sputtered on the resistive switching layer.

The present invention is suitable to the field of electronic technology, and provides a method of manufacturing a thin film transistor and a pixel unit thereof, wherein when the thin film transistor is manufactured, the gate metal layer is used as a mask, and exposed from the back of the substrate to position the channel and the source and drain of the thin film transistor, so that the channel is self-aligned with the gate, and the source and drain are self-aligned with the gate and are symmetrical, and the thin film transistor thus manufactured has a small parasitic capacitance, and the circuit manufactured therewith is fast in operation, and less prone to occurring short circuit or open circuit. In the present invention, the characteristics that the channel is self-aligned with the gate, and the source and drain are self-aligned with the gate and are symmetrical avoid the alignment precision requirement on the mask plate in the production, thus reducing the need for the high precision lithographic apparatus, and reducing the costs and increasing the yield. In addition, the present process is suitable for manufacturing a pixel unit of a thin film transistor, the manufacturing process only requires four mask sets which do not require the critical alignment. As compared with other four mask processes which use the gray tone masks, the present process can increase the yield and reduce the costs.

The invention provides a thin film transistor, an array substrate and a display device. The thin film transistor comprises a conductive oxygen vacancy reducing layer for reducing oxygen vacancies in an active layer. The oxygen vacancy reducing layer is disposed between the active layer and a source and/or the active layer and a drain. With the oxygen vacancy reducing layer, the number of the oxygen vacancies in the active layer is decreased greatly, which improves transmission rate of carriers and simultaneously reduces value of subthreshold swing of the thin film transistor.

A method and apparatus for manufacturing a lattice structure of a material on a substrate, wherein the process may be performed at atmospheric pressure, may not require a metallic substrate, may be capable of continuously generating the lattice structure as long as desired, may be as thin as a single layer of the lattice material, and may create the lattice structure with any material that is capable of being vaporized to create a stream of ionized particles and then condensed to form the lattice structure.

A manufacturing method and a manufacturing equipment of a thin film transistor substrate are provided. In the manufacturing method, after forming a gate and a gate insulating layer of a thin film transistor, a semiconductor layer and a first protection layer are sequentially deposited. After patterning the first protection layer, the patterned first protection layer is used as a mask to pattern the semiconductor layer to form a semiconductor channel of the thin film transistor. By the above solution, the invention can reduce the number of mask and therefore is beneficial to reduce the cost.

To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed, a semiconductor device includes a first conductive layer over an insulating layer, a semiconductor layer over the first conductive layer, a second conductive layer over the semiconductor layer, a gate insulating layer over the second conductive layer, and a gate electrode over the gate insulating layer. The semiconductor device may further include wiring layers. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 110.sup.13 A or less per micrometer in channel width, and may be 110.sup.17 A or less per micrometer. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.