A semiconductor structure is provided that includes a silicon germanium alloy fin located on a portion of a topmost surface of an insulator layer. A functional gate structure straddles a portion of the silicon germanium alloy fin and is located on other portions of the topmost surface of the insulator layer. A source structure is located on one side of the functional gate structure and a drain structure is located on another side of the functional gate structure. The source structure and the drain structure surround the other portions of the silicon germanium alloy fin and are located on a germanium graded silicon-containing region that is present at a footprint of the other portions of the silicon germanium alloy fin.

In one embodiment, a method of manufacturing a semiconductor device includes forming a first semiconductor layer including impurity atoms with a first density, on a first substrate, forming a second semiconductor layer including impurity atoms with a second density higher than the first density, on the first semiconductor layer, and forming a porous layer resulting from porosification of at least a portion of the second semiconductor layer. The method further includes forming a first film including a device, on the porous layer, providing a second substrate provided with a second film including a device, and bonding the first and second substrates to sandwich the first and second films. The method further includes separating the first and second substrates from each other such that a first portion of the porous layer remains on the first substrate and a second portion of the porous layer remains on the second substrate.

A wafer bonding technique to fabricate GaN devices is disclosed. In this technique, a GaN layer (or a GaN stack including at least one GaN layer) is fabricated on a first substrate (e.g., a silicon substrate) and has a high quality surface with a dislocation density less than 10.sup.10/cm.sup.2. The assembly of the first substrate and the GaN layer is then bonded to a second substrate (e.g., a carbide substrate or an AlN substrate) by coupling the high quality surface to the second substrate. The high quality of the GaN surface in contact with the carbide substrate creates a good thermal contact. The first substrate is etched away to expose a GaN surface for further processing, such as electrode formation.

Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.

An inspection system for a semiconductor package includes an inspection apparatus that includes a stage on which the semiconductor package is loaded, and a computer coupled to the inspection apparatus. The semiconductor package may include a first semiconductor chip and a second semiconductor chip on the first semiconductor chip, the computer may provide first identification information about the first semiconductor chip and second identification information about the second semiconductor chip, and the computer may control the inspection apparatus to selectively perform a package test process on one of the first and second semiconductor chips, the one of the first and second semiconductor chips being identified as a good chip based on the first identification information and the second identification information.

A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

The present invention relates to a substrate aligning device for bonding a first substrate (100) and a second substrate (200), wherein the first substrate (100) and the second substrate (200) have respective bonding surfaces via which the first substrate (100) and the second substrate (200) are bonded face-to-face with each other, and respective non-bonding surfaces which are located on the reverse sides from the bonding surfaces. The substrate alignment device comprises: a first substrate (100) having a first bonding surface (110) and a first non-bonding surface (120) located on the reverse side from the first bonding surface (110); a second substrate (200) having a second bonding surface (210) and a second non-bonding surface (220) located on the reverse side from the second bonding surface (210); a first holder (300) formed such that the first non-bonding surface (120) of the first substrate (100) is seated thereon; and a second holder (400) formed such that the second non-bonding surface (220) of the second substrate (200) is seated thereon. The first substrate (100) and the second substrate (200) are aligned by bringing the first holder (300) and the second holder (400) toward each other so that the first bonding-surface (110) and the second bonding-surface (210) come into close contact with each other. Since the alignment can be achieved without penetrating an opaque substrate, existing fine alignment limitations can be eliminated, and misalignment can be prevented.

A method for manufacturing a semiconductor device includes: providing a carrier wafer and a silicon carbide wafer; bonding a first side of the silicon carbide wafer to the carrier wafer; splitting the silicon carbide wafer bonded to the carrier wafer into a silicon carbide layer thinner than the silicon carbide wafer and a residual silicon carbide wafer, the silicon carbide layer remaining bonded to the carrier wafer during the splitting; and forming a graphene material on the silicon carbide layer.

A method provides a first substrate supporting an insulator layer having trenches formed therein; filling the trenches using an epitaxial growth process with at least semiconductor material; planarizing tops of the filled trenches; forming a first layer of dielectric material on a resulting planarized surface; inverting the first substrate wafer to place the first layer of dielectric material in contact with a second layer of dielectric material on a second substrate; bonding the first substrate to the second substrate through the first and second layers of dielectric material to form a common layer of dielectric material; and removing the first substrate and a first portion of the filled trenches to leave a second portion of the filled trenches disposed upon the common dielectric layer. The removed first portion of the filled trenches contains dislocation defects. The method then removes the insulator layer to leave a plurality of Fin structures.

A method of forming a semiconductor structure that includes compressive strained silicon germanium alloy fins having a first germanium content and tensile strained silicon germanium alloy fins having a second germanium content that is less than the first germanium content is provided. The different strained and germanium content silicon germanium alloy fins are located on a same substrate. The method includes forming a cladding layer of silicon around a set of the silicon germanium alloy fins, and forming a cladding layer of a germanium containing material around another set of the silicon germanium alloy fins. Thermal mixing is then employed to form the different strained and germanium content silicon germanium alloy fins.