A method for bonding a first substrate with a second substrate at respective contact faces of the substrates with the following steps: holding the first substrate to a first sample holder surface of a first sample holder with a holding force F.sub.H1 and holding the second substrate to a second sample holder surface of a second sample holder with a holding force F.sub.H2; contacting the contact faces at a bond initiation point and heating at least the second sample holder surface to a heating temperature T.sub.H; bonding of the first substrate with the second substrate along a bonding wave running from the bond initiation point to the side edges of the substrates, wherein the heating temperature T.sub.H is reduced at the second sample holder surface during the bonding.

An engineered substrate comprising: a seed layer made of a first semiconductor material for growth of a solar cell; a first bonding layer on the seed layer; a support substrate made of a second semiconductor material; a second bonding layer on a first side of the support substrate; a bonding interface between the first and second bonding layers; the first and second bonding layers each made of metallic material; wherein doping concentration and thickness of the engineered substrate, in particular, of the seed layer, the support substrate, and both the first and second bonding layers, are selected such that the absorption of the seed layer is less than 20%, preferably less than 10%, as well as total area-normalized series resistance of the engineered substrate is less than 10 mOhm.Math.cm.sup.2, preferably less than 5 mOhm.Math.cm.sup.2.

A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor formed at a front side of the semiconductor substrate. The DTMOS transistor includes a gate electrode, and a source/drain region adjacent to the gate electrode. The source/drain region is disposed in the well region. A well pickup region is in the well region, and the well pickup region is at a back side of the semiconductor substrate. The well pickup region is electrically connected to the gate electrode.

Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

An electromagnetic wave irradiation apparatus and methods to bond unbonded areas in a bonded pair of substrates are disclosed. The unbonded areas between the substrates are eliminated by thermal activation in the unbonded areas induced by electromagnetic wave irradiation having a wavelength selected to effect a phonon or electron excitation. A first substrate of the bonded pair of substrates absorbs the electromagnetic radiation and a portion of a resulting thermal energy transfers to an interface of the bonded pair of substrates at the unbonded areas with sufficient flux to cause opposite sides the first and second substrates to interact and dehydrate to form a bond (e.g., Si—O—Si bond).

A spalling process can be employed to generate a fracture at a predetermined depth within a high quality crystalline nitride substrate, such as a bulk GaN substrate. A first crystalline conductive film layer can be separated, along the line of fracture, from the crystalline nitride substrate and subsequently bonded to a layered stack including a traditional lower-cost substrate. If the spalled surface of the first crystalline conductive film layer is exposed in the resulting structure, the structure can act as a substrate on which high quality GaN-based devices can be grown.

The disclosed technology relates generally to a method and system for micro assembling GaN materials and devices to form displays and lighting components that use arrays of small LEDs and high-power, high-voltage, and or high frequency transistors and diodes. GaN materials and devices can be formed from epitaxy on sapphire, silicon carbide, gallium nitride, aluminum nitride, or silicon substrates. The disclosed technology provides systems and methods for preparing GaN materials and devices at least partially formed on several of those native substrates for micro assembly.

Provided is an SiC composite substrate 10 having a monocrystalline SiC layer 12 on a polycrystalline SiC substrate 11, wherein: some or all of the interface at which the polycrystalline SiC substrate 11 and the monocrystalline SiC layer 12 are in contact is an unmatched interface I.sub.12/11 that is not lattice-matched; the monocrystalline SiC layer 12 has a smooth obverse surface and has, on the side of the interface with the polycrystalline SiC substrate 11, a surface that has more pronounced depressions and projections than the obverse surface; and the close-packed plane (lattice plane 11p) of the crystals of the polycrystalline SiC in the polycrystalline SiC substrate 11 is randomly oriented with reference to the direction of a normal to the obverse surface of the monocrystalline SiC layer 12. The present invention improves the adhesion between the polycrystalline SiC substrate and the monocrystalline SiC layer.

According to an embodiment, a sensor package includes an electrically insulating substrate including a cavity in the electrically insulating substrate, an ambient sensor, an integrated circuit die embedded in the electrically insulating substrate, and a plurality of conductive interconnect structures coupling the ambient sensor to the integrated circuit die. The ambient sensor is supported by the electrically insulating substrate and arranged adjacent the cavity.

A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.