An electronic device is disclosed and includes a conductive layer, a first dielectric layer, and a second dielectric layer, in which the second dielectric layer is disposed on the first dielectric layer, the conductive layer is disposed between the first dielectric layer and the second dielectric layer, the first dielectric layer has a first transmittance for a light, the second dielectric layer has a second transmittance for the light, and the first transmittance is different from the second transmittance.

The invention discloses a semiconductor package structure including a package carrier, at least one electronic component, a packaging layer, a support component and a shielding layer. The electronic component is disposed on a first surface of the package carrier. The packaging layer is disposed on the first surface and covers the electronic component. The support component is embedded in the packaging layer to surround the electronic component. An end surface of the support component is electrically connected to a build-up circuit and electrically grounded. A patterned metal layer of the shielding layer is electrically connected to the support component. The shielding range of the patterned metal layer covers at least electronic component. A shielding space, which covers the electronic component, is formed by the support component and the shielding layer. In addition, a semiconductor EMI shielding component and a method of making a semiconductor package structure are also disclosed.

An electronic carrier and a method of manufacturing an electronic carrier are provided. The electronic carrier includes a first interconnection structure and a second interconnection structure. The first interconnection structure includes a first patterned conductive layer having a first pattern density. The second interconnection structure is laminated to the first interconnection structure and includes a second patterned conductive layer having a second pattern density higher than the first pattern density. The first interconnection structure is electrically coupled to the second interconnection structure through a first non-soldering joint between and outside of the first interconnection structure and the second interconnection structure.

A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.

A semiconductor device of an embodiment includes a plurality of chip regions, each including a memory region in which a plurality of memory cells is arranged, and a kerf region disposed between the chip regions and surrounding each chip region. Paired marks are arranged in a vicinity of the memory region of one of the plurality of chip regions and in a common hierarchical layer in the kerf region, and the paired marks are disposed over upper and lower hierarchical layers.

A semiconductor device of an embodiment includes a plurality of chip regions, each including a memory region in which a plurality of memory cells is arranged, and a kerf region disposed between the chip regions and surrounding each chip region. Paired marks are arranged in a vicinity of the memory region of one of the plurality of chip regions and in a common hierarchical layer in the kerf region, and the paired marks are disposed over upper and lower hierarchical layers.

A package device and a manufacturing method thereof are provided. The package device includes a redistribution layer including a first dielectric layer, a conductive layer, and a second dielectric layer. The conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test mark, the test mark includes a plurality of conductive patterns formed of the conductive layer, and the conductive patterns are arranged in a ring shape.

A circuit module (e.g., an amplifier module) includes a module substrate, a thermal dissipation structure, a semiconductor die, encapsulant material, and an interposer. The module substrate has a mounting surface and a plurality of conductive pads at the mounting surface. The thermal dissipation structure extends through the module substrate, and a surface of the thermal dissipation structure is exposed at the mounting surface of the module substrate. The semiconductor die is coupled to the surface of the thermal dissipation structure. The encapsulant material covers the mounting surface of the module substrate and the semiconductor die, and a surface of the encapsulant material defines a contact surface of the circuit module. The interposer is embedded within the encapsulant material. The interposer includes a conductive terminal with a proximal end coupled to a conductive pad of the module substrate, and a distal end exposed at the contact surface of the circuit module.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the surface of the package substrate; and a cooling apparatus that may include a conductive base having a first surface and an opposing second surface, wherein the first surface of the conductive base is in thermal contact with the second surface of the die, and a plurality of conductive structures on the second surface of the conductive base, wherein an individual conductive structure of the plurality of conductive structures has a width between 10 microns and 100 microns.

An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.