An orientation chamber is provided. The orientation chamber includes a substrate holder, an orientation detector, and a purging system. The substrate holder is configured to hold a substrate. The orientation detector is configured to detect an orientation of the substrate. The purging system is configured to inject a cleaning gas into the orientation chamber and remove contaminants from the substrate. The purging system includes a gas regulator adjusting a volume of the cleaning gas supplied into the orientation chamber according to a detection signal output from a gas detector which indicates a content of a specific gas contaminant outgassed from the substrate.

In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.

Embodiments of the present disclosure relate a CMP tool and methods for planarization a substrate. Particularly, embodiments of the present disclosure provide a substrate transporter for use in a CMP tool. The transporter may be used transport and/or carry substrates among various polishers and cleaners in a CMP tool while preventing the substrates from drying out during transportation. By keeping surfaces of the substrates wet during substrate waiting time or idle time in the CMP tool, embodiments of the present disclosure prevent many types of defects, such as byproducts, agglomerated abrasives, pad debris, slurry residues, from accumulate on the substrate surface during CMP processing, thus improve yields and device performance.

A method of forming a semiconductor package includes providing a panel, providing one or more metal layers on an upper surface of the panel, forming a die pad and bond pads from the one or more metal layers, the die pad being adjacent to and spaced apart from the bond pads, attaching a die to the die pad, forming electrical connections between the die and the bond pads, encapsulating the die and the electrical connections with an electrically insulating mold compound, removing portions of the panel, and exposing the die pad and the bond pads after encapsulating the die.

A heating device is provided. The heating device includes a conveyance member that conveys a substrate between a heating position and a non-heating position, a support member that is provided on the conveyance member and that supports the substrate, a heater provided at the heating position and operable to heat a first surface of the substrate, and a heat reflecting plate attached to the conveyance member in facing relation to a second surface of the substrate opposite to the first surface.

This disclosure relates to a high volume manufacturing system for processing and measuring workpieces in a semiconductor processing sequence without leaving the system's controlled environment (e.g., sub-atmospheric pressure). The system includes an active interdiction control system to implement corrective processing within the system when a non-conformity is detected. The corrective processing can include a remedial process sequence to correct the non-conformity or compensate for the non-conformity during subsequent process. The non-conformity may be associated with fabrication measurement data, process parameter data, and/or platform performance data.

A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.

A system for maintaining a device in a semiconductor manufacturing environment that includes a controller configured to determine a distance travelled by the device within the semiconductor manufacturing environment, where the device has a feature that selectively engages a carrier configured to carry a semiconductor wafer such that the device moves the semiconductor wafer to different processing stations within the semiconductor manufacturing environment. The system also includes an inspection component configured to inspect the device responsive to the distance travelled by the device exceeding a distance threshold, a repair component configured to repair the device responsive to a repair indication from at least one of the controller or the inspection component, and a cleaning component configured to clean the device responsive to a clean indication from at least one of the controller or the inspection component.

A method of manufacturing a semiconductor package and a semiconductor package in which positional alignment between a wafer and a substrate until the wafer is mounted and packaged on the substrate is achieved accurately. A wafer is mounted on a package substrate by using first alignment marks and D-cuts as benchmarks, and then a mold resin layer is formed on the wafer in a state in which the first alignment mark is exposed. A part of the mold resin layer is removed by using the D-cuts exposed from the mold resin layer as benchmarks, so that the first alignment marks can be visually recognized. A second alignment marks are formed on the mold resin layer by using the first alignment marks as benchmarks. A Cu redistribution layer to be conducted to a pad portion is formed on a mold resin layer by using the second alignment marks as benchmarks.

A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.