In one embodiment, a capacitor includes a first row including a first capacitor element and a second capacitor element coupled in parallel, and a second row including a third capacitor element and a fourth capacitor element coupled in parallel. The first row is coupled in series with the second row. In a metallization level over a workpiece, the second capacitor element is disposed between the first capacitor element and the third capacitor element. In the metallization level, the third capacitor element is disposed between the second capacitor element and the fourth capacitor element. The first, the second, the third, and the fourth capacitor elements are disposed in the metallization level.

A method of fabricating a radio-frequency multi-layer circuit includes perforating a silicon wafer to form a plurality of perforations, forming a plurality of vias spaced apart by the plurality of perforations, oxidizing the silicon wafer to provide a silicon oxide wafer, after forming the plurality of vias, filling the plurality of perforations with a fused silica layer to convert the silicon oxide wafer into a fused silica wafer, depositing within the plurality of vias and between the plurality of vias a metal layer connector to electrically connect the plurality of vias, and bonding two or more fused silica wafers together such that the vias of the two or more fused silica wafers are electrically connected to each other to form a radio-frequency circuit.

Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

A semi-conductor structure with selective bottom terminal contacting is described. The semiconductor device comprises a first metal layer disposed over a substrate; a conductive layer disposed over the first metal layer; and a second metal layer disposed over the conductive layer, the second metal layer embedding a porous structure comprising a plurality of pores that extend substantially perpendicularly from a top surface of the porous structure toward the conductive layer, wherein only a subset of the plurality of pores open onto the conductive layer.

A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.

A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.

Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

An integrated circuit (IC) substrate manufacturing process provides time-dependent device characteristic variation due to hydrogen absorption by including one or more gettering layers near the devices that would otherwise absorb hydrogen and exhibit the variation as the hydrogen migrates in the devices. The method includes forming or mounting the devices on a top surface of the semiconductor wafer in die areas of the substrate, forming semiconductor structures in the semiconductor die areas, forming a getter layer above or adjacent to the devices in the die areas, and processing the wafer with one or more processes exposing the wafer to vapor having a hydrogen content, whereby an amount of hydrogen absorbed by the devices is reduced by presence of the getter layer. The method produces wafers including semiconductor dies with reduced hydrogen absorption by the devices and packaged ICs including the dies.

A method and an electronic device that includes an isolation structure having a dielectric material on or in a semiconductor surface layer, and a passive circuit component having a metal silicide structure on a side of the isolation structure, there the metal silicide structure includes a metal silicide portion and a dielectric portion, the dielectric portion of the metal silicide structure including one of silicon nitride, silicon oxide, silicon carbide, silicon carbon nitride, and silicon oxynitride. The method includes forming a dielectric material of the isolation structure on or in the semiconductor surface layer, forming a silicon-rich dielectric layer on a side of the isolation structure, and siliciding the silicon-rich dielectric layer to form the metal silicide structure on the side of the isolation structure.