An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

According to various embodiments, an integrated circuit may include an upper inter-level dielectric (ILD) layer, a lower ILD layer, and an interlayer arranged between the upper ILD layer and the lower ILD layer. The integrated circuit may further include a capacitor device and a resistor device. The capacitor device may include a top plate disposed in a first region of the interlayer and a bottom plate disposed in the lower ILD layer. The resistor device may include a resistive element and a plurality of vias disposed in a second region of the interlayer. The plurality of vias may extend from the resistive element to the lower ILD layer. A distance between the top plate and the lower ILD layer may be at least substantially equal to a height of each via of the plurality of vias.

Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

Disclosed herein is an electronic component that includes a substrate, a functional layer formed on the substrate and having a plurality of alternately stacked conductor layers and insulating layers, and a plurality of terminal electrodes provided on an uppermost one of the insulating layers. The uppermost one of the insulating layers has a substantially rectangular planar shape and has a protruding part protruding in a planar direction from at least one side in a plan view.

Short-wave infrared (SWIR) focal plane arrays (FPAs) comprising a Si layer through which light detectable by the FPA reaches photodiodes of the FPA, at least one germanium (Ge) layer including a plurality of distinct photosensitive areas including at least one photosensitive area in each of a plurality of photosensitive photosites, each of the distinct photosensitive areas comprising a plurality of proximate steep structures of Ge having height of at least 0.5 μm and a height-to-width ratio of at least 2, and methods for forming same.

A multi-color display includes a backplane having backplane circuitry, an array of micro-LEDs electrically integrated with backplane circuitry of the backplane, a color conversion layer over each of a plurality of light emitting diodes, and a plurality of isolation walls separating adjacent micro-LEDs of the array.

A system-on-chip may include an inductor-capacitor oscillator monolithically integrated into the system-on-chip The inductor-capacitor oscillator may be configured to improve frequency stability and reduce noise when compared to a resistor-capacitor oscillator. Methods of making integrated oscillators may involve forming an inductor at least partially while forming a BEOL structure on a substrate. A capacitor supported on and/or embedded within the semiconductor material of the substrate may be formed before or while forming the BEOL structure. The inductor may be connected to the capacitor in parallel at least partially utilizing the BEOL structure to form an integrated inductor-capacitor oscillator.

An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

RC architectures are provided that include a substrate provided with a capacitor having a thin-film top electrode portion at a surface of the substrate on one side thereof. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion, and a set of plural bridging contacts extending between, and electrically interconnecting, the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The capacitor can be a three-dimensional capacitor and contacts are then provided on respective first and second sides of the substrate, which face each other in the thickness direction of the substrate.

An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.