A method of manufacturing a package structure includes: forming a backside RDL structure on a carrier; forming TIVs on the backside RDL structure; mounting at least one passive device on the backside RDL structure, so that the at least one passive device is disposed between the TIVs; placing a die on the at least one passive device, so that the at least one passive device is vertically sandwiched between the die and the backside RDL structure; forming an encapsulant laterally encapsulating the die, the TIVs, and the at least one passive device; forming a front side RDL structure on a front side of the die, the TIVs, and the encapsulant; releasing the backside RDL structure from the carrier; and mounting a package on the backside RDL structure, wherein the package is electrically connected to the at least one passive device by conductive connectors and solders.

A semiconductor device includes a substrate having first fin and a second fin spaced apart and extending lengthwise in parallel. A fin remnant is disposed between the first fin and the second fin, extends lengthwise in parallel with the first and second fins, and has a height lower than a height of each of the first fin and the second fin. A first field insulation layer is disposed between a sidewall of the first fin and a first sidewall of the fin remnant and a second field insulating layer is disposed on a sidewall of the second fin. A blocking liner conforms to a sidewall and a bottom surface of a trench bounded by a second sidewall of the fin remnant and a sidewall of the second field insulating layer. A trench insulation layer is disposed on the blocking liner in the trench.

Embodiments of the disclosure provide a semiconductor structure and a method for forming the same. The semiconductor structure includes: a semiconductor substrate including a plurality of active areas and first isolation structures arranged at intervals along a first direction; gate structures located in the active areas and the first isolation structures. Top surfaces of the active areas extend beyond top surfaces of the gate structures; second isolation structures with a preset height located on surfaces of the gate structures, and the top surfaces of the second isolation structures are flush with the top surfaces of the active areas.

Embodiments of bonded unified semiconductor chips and fabrication and operation methods thereof are disclosed. In an example, a method for forming a unified semiconductor chip is disclosed. A first semiconductor structure is formed. The first semiconductor structure includes one or more processors, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

Embodiments of bonded unified semiconductor chips and fabrication and operation methods thereof are disclosed. In an example, a method for forming a unified semiconductor chip is disclosed. A first semiconductor structure is formed. The first semiconductor structure includes one or more processors, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.

An integrated circuit (IC) structure includes an active device over a bulk semiconductor substrate, and an isolation structure around the active device in the bulk semiconductor substrate. The active device includes a semiconductor layer having a center region, a first end region laterally spaced from the center region by a first trench isolation, a second end region laterally spaced from the center region by a second trench isolation, a gate over the center region, and a source/drain region in each of the first and second end regions. The isolation structure includes: a polycrystalline isolation layer under the active device, a third trench isolation around the active device, and a porous semiconductor layer between the first trench isolation and the polycrystalline isolation layer and between the second trench isolation and the polycrystalline isolation layer.

A technique to make silicon oxide regions from porous silicon and related semiconductor structures is disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

A method for manufacturing a semiconductor device includes forming a source region, a drain region, and a gate dielectric layer and a gate electrode covering a channel region between the source region and the drain region, forming an insulating layer over the source region, the drain region, and the gate electrode, forming first to third vias penetrating the insulating layer and exposing portions of the source region, the drain region, and the gate electrode, respectively, forming a source contact in the first via to electrically connect to the source region, forming a drain contact in the second via to electrically connect to the drain region, and forming a gate contact in the third via to electrically connect to the gate electrode. One or more of the first to third vias is formed by ion bombarding by a focused ion beam and followed by a thermal annealing process.