A method includes forming a plurality of first line-shaped mask patterns over a substrate including a memory cell region and an array edge region; forming a plurality of second line-shaped mask patterns over the plurality of first line-shaped mask patterns; removing first portions from the plurality of first line-shaped mask patterns in the memory cell region to leave a plurality of island-shaped mask patterns above the memory cell region; removing second portions from the plurality of first line-shaped mask patterns in the array edge region to leave a holes-provided mask pattern above the array edge region; forming a mask pattern which includes a plurality of holes provided on portions; and forming, with the mask pattern which includes the plurality of holes, a plurality of contact holes in the array edge region to provide a plurality of contact electrodes connected to a plurality of word-lines.

A semiconductor structure, including a plurality of connection patterns disposed on the substrate, and a merged pattern disposed between adjacent two of the connection patterns, wherein the merged pattern includes a first outer line, a central line and a second outer line sequentially arranged along a first direction and connected with each other, and an end surface of the first outer line, an end surface of the central line and an end surface of the second outer line are misaligned along the first direction.

An exemplary device includes a dielectric layer and a transmission line structure disposed in the dielectric layer. The transmission line structure includes a first metal line disposed between a second metal line and a third metal line. Dielectric islands are disposed in a first region and a second region of the dielectric layer. The first region of the dielectric layer is between the first metal line and the second metal line. The second region of the dielectric layer is between the first metal line and the third metal line. A dielectric constant of the dielectric islands is greater than a dielectric constant of the dielectric layer. The dielectric islands may be doped sections of the dielectric layer. In some embodiments, the dielectric islands in the first region are aligned with the dielectric islands in the second region along a direction perpendicular to a lengthwise direction of the first metal line.

A method of forming a metal superlattice structure includes depositing, on a substrate, a layer of a first metal with face-centered-cubic (fcc) crystal structure. The method further includes depositing a layer of ruthenium (Ru) metal with fcc crystal structure on the layer of the first metal. The layer of the first metal may cause the layer of ruthenium metal to have fcc crystal structure.

A variety of applications can include apparatus having a memory device with an array of vertical strings of memory cells for the memory device with data lines coupled to the vertical strings, where the data lines have been formed by a metal liner deposition process. In the metal liner deposition, a metal can be formed on a patterned dielectric region. The metal liner deposition process allows for construction of the height of the data lines to be well controlled with selection of a thickness for the dielectric region used in forming the metal liner. Use of a metal liner deposition provides a controlled mechanism to reduce data line capacitance by being able to select liner thickness in forming the data lines. The use of the dielectric region with the metal liner deposition can allow the fabrication of the data lines to avoid pitch double or pitch quad processes.

A semiconductor structure includes: a semiconductor substrate; a first metal layer located on a surface of the semiconductor substrate; a second metal layer located above a surface of the first metal layer; an insulating layer located between the first metal layer and the second metal layer and configured to isolate the first metal layer from the second metal layer; and at least four vias located in the insulating layer and a conductive material for connecting the first metal layer and the second metal layer is filled in the at least four vias.

A method for fabricating a semiconductor device includes: forming a stack body over a substrate; forming channel structures in the stack body, the channel structures comprising a channel layer penetrating the stack body; forming a contact-level dielectric layer over the stack body and the channel structures; forming a contact hole penetrating the contact-level dielectric layer; forming contact plugs in the contact hole, the contact plugs coupled to the channel layers of the channel structures; recessing the contact plugs to form upper surfaces of the contact plugs that are lower than an upper surface of the contact-level dielectric layer; forming a bit line-level dielectric layer including a spacer layer over the recessed contact plugs; etching the bit line-level dielectric layer to form trenches that expose the recessed contact plugs; and forming a bit line in one or more of the trenches.

A semiconductor device includes active regions extending in a first direction on a substrate; a gate electrode intersecting the active regions on the substrate, extending in a second direction, and including a contact region protruding upwardly; and an interconnection line on the gate electrode and connected to the contact region, wherein the contact region includes a lower region having a first width in the second direction and an upper region located on the lower region and having a second width smaller than the first width in the second direction, and wherein at least one side surface of the contact region in the second direction has a point at which an inclination or a curvature is changed between the lower region and the upper region.

A semiconductor device structure is provided. The semiconductor device structure includes a gate stack and a source/drain contact structure formed over a substrate. A first gate spacer is separated the gate stack from the source/drain contact structure and extends above top surfaces of the gate stack and the source/drain contact structure. An insulating capping layer covers the top surface of the gate stack and extends on the top surface of the first gate spacer. A conductive via structure partially covers the top surface of the insulating capping layer and the top surface of the source/drain contact structure. A first insulating layer surrounds the conductive via structure and partially covers the top surface of the source/drain contact structure.

A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.