A method for manufacturing an array substrate includes forming a buffer layer on a substrate; forming a source and a data line in the buffer layer, forming a first gate, a second gate, a first scan line, and a second scan line on the buffer layer, simultaneously; forming a semiconductor layer; forming a conductor layer by converting the semiconductor layer formed on the first scan line and the second scan line into a conductor; forming a first pixel electrode on the semiconductor layer and forming a second pixel electrode on the conductor layer, simultaneously.

The invention discloses a MOS transistor for suppressing generation of a photo-induced leakage current in an active channel region, and an application thereof. A fabrication process comprises: forming a source and a drain at both ends of a substrate by ion implantation, fabricating a gate oxide layer in a middle of an upper surface of the substrate; depositing a polysilicon or a metal on the gate oxide layer to form a gate; depositing an isolation layer above the gate, the source, and the drain; etching contact holes above the source and the drain to extract the source and the drain; depositing the metal on the contact holes above the source and the drain; etching the metal on the drain to isolate the source from the drain; and enabling the metal on the source to directly extend to cover the active channel region, so as to block light rays. The MOS transistor proposed by the invention effectively blocks the light rays incident from above the MOS transistor, suppresses generation of the photo-induced leakage current, not only improves off-state characteristics of the transistor, but also improves a working performance of an active address driving circuit.

A thin film transistor array panel, including: a first insulating substrate; a gate line disposed on the first insulating substrate and including a gate electrode; a semiconductor layer disposed on the gate electrode; a data conductor layer disposed on the semiconductor layer, and including a data line crossing the gate line, a source electrode connected to the data line and exposing at least a part of the semiconductor layer, and a drain electrode facing the source electrode; a capping layer disposed on the data conductor layer, the semiconductor layer exposed between the source electrode and the drain electrode, and the entire surface of the first insulating substrate; and a first passivation layer disposed on the capping layer. The capping layer and the semiconductor layer include the same material.

An LCD device includes a TFT array substrate, a liquid crystal layer, and a plurality of photo spacers. The photo spacers are located inside the liquid crystal layer. The TFT array substrate includes a pixel electrode layer and an alignment layer. The alignment layer is arranged on the of TFT array substrate on the side near the liquid crystal layer. The pixel electrode layer is arranged on the alignment layer on the side far away from liquid crystal layer; the alignment layer includes a plurality of contact portion. The bottom of the photo spacers are holding with the contact portions. A plurality of block portion is adjacent to the contact portions. The block portion is a protrusion formed toward the color filter substrate with respect to the contact portion, so that the displacement of the photo spacers on the TFT array substrate can be limited.

An array substrate, a manufacturing method thereof and a display device. The array substrate includes a substrate, a thin film transistor on the substrate, and including an active layer including a source region, a drain region and a channel region between the source region and the drain region; a heat dissipation layer disposed between the substrate and the drain region; and the orthographic projection of the heat dissipation layer on the substrate at least covers the orthographic projection of a part of the source region and a part of the drain region on the substrate. The manufacturing method is for the manufacturing of the array substrate. The array substrate can improve the sizes and uniformity of the crystal particles.

A control method for differentiated etching depth is provided. The method includes: providing a first etching stop pattern layer in a panel having stacked structure; adopting a first etchant to perform a first etching process to the panel such that a location of the panel provided with the first etching stop pattern layer forms a first etching depth, and forms a second etching depth at a location of the panel without providing the first etching stop pattern layer; through controlling an etching time, the second etching depth is deeper than a bottom of the first etching stop pattern layer; and adopting a second etchant to perform a second etching process to the panel in order to etch and remove the first etching stop pattern layer. In a same mask process, through changing the etchant, different depths are etched and formed to reduce the time consuming and decrease the production cost.

The present disclosure provides a circuit for processing a voltage of a pixel electrode and a display apparatus. The circuit for processing a voltage of a pixel electrode comprises: a first input terminal configured to input an original voltage of the pixel electrode; a second input terminal configured to input a voltage of a common electrode; and an output terminal configured to output a processed voltage of the pixel electrode, wherein the circuit for processing a voltage of a pixel electrode is configured to superimpose the voltage of the common electrode on the original voltage of the pixel electrode, to acquire a voltage which is stable with respect to the voltage of the common electrode as the processed voltage of the pixel electrode.

The present disclosure provides an array substrate for a display device and a manufacturing method thereof. A transparent electrode pattern (ITO) may be formed between a source/drain metal pattern and a passivation layer located above the source/drain metal pattern, which are formed in a passivation hole area of a non-active area of the array substrate. Accordingly, it may be possible to prevent display failure caused by a delamination phenomenon or peel-off of a material of the passivation layer due to the lack of adhesion strength between a metal layer and the passivation layer in the passivation hole area.

Provided is a flexible device with fewer defects caused by a crack or a flexible device having high productivity. A semiconductor device including: a display portion over a flexible substrate, including a transistor and a display element; a semiconductor layer surrounding the display portion; and an insulating layer over the transistor and the semiconductor layer. When seen in a direction perpendicular to a surface of the flexible substrate, an end portion of the substrate is substantially aligned with an end portion of the semiconductor layer, and an end portion of the insulating layer is positioned over the semiconductor layer.

The present invention provides a method and a device for releasing film layer stress of an array substrate. In the method for releasing film layer stress of an array substrate, the array substrate is positioned, in a still condition, on a carrying table involving an arc surface and a carrying table curvature adjusting mechanism is operated to gradually vary the curvature of the arc surface of the carrying table such that the array substrate, under the action of the gravity, is caused to curve according to the arc surface of the carrying table and the degree of curving varies following the variation of the curvature of the arc surface of the carrying table so as to make each film layer of the array substrate exhibiting uniform tension stress or compression stress, and eventually, the stress accumulated among the film layers of the array substrate during a manufacturing process can be released through the action of the external force, thereby reducing the influence that an external pressure causes on the property of a device provided on the array substrate during a subsequent process and uses thereof, so as to reduce poor displaying of a display panel and ensure product yield.