A manufacturing method of a semiconductor package includes etching a first surface and a side surface of a base substrate, the base substrate including the first, a second and the side surfaces positioned between the first and the second surfaces, the base substrate containing a metal, attaching a metal different from the metal contained in the base substrate to the first and the side surfaces, disposing a semiconductor device on the second surface, the semiconductor device having an external terminal, forming a resin insulating layer sealing the semiconductor device, forming a first conductive layer on the resin insulating layer, forming an opening, exposing the external terminal, in the first conductive layer and the resin insulating layer; and forming a metal layer on the first and the side surfaces, on the first conductive layer and in the opening.

Circuit board includes conductive plate, core dielectric layer, metallization layer, first build-up stack, second build-up stack. Conductive plate has channels extending from top surface to bottom surface. Core dielectric layer extends on covering top surface and side surfaces of conductive plate. Metallization layer extends on core dielectric layer and within channels of conductive plate. Core dielectric layer insulates metallization layer from conductive plate. First build-up stack is disposed on top surface of conductive plate and includes conductive layers alternately stacked with dielectric layers. Conductive layers electrically connect to metallization layer. Second build-up stack is disposed on bottom surface of conductive plate. Second build-up stack includes bottommost dielectric layer and bottommost conductive layer. Bottommost dielectric layer covers bottom surface of conductive plate. Bottommost conductive layer is disposed on bottommost dielectric layer and electrically connects to metallization layer. First build-up stack includes more conductive and dielectric layers than second build-up stack.

Heat spreading substrate with embedded interconnects. In an embodiment in accordance with the present invention, an apparatus includes a metal parallelepiped comprising a plurality of wires inside the metal parallelepiped. The plurality of wires have a different grain structure than the metal parallelepiped. The plurality of wires are electrically isolated from the metal parallelepiped. The plurality of wires may be electrically isolated from one another.

An insulated metal substrate (IMS) and a method for manufacturing the same are disclosed. The IMS includes an electrically conductive line pattern layer, an encapsulation layer, a first adhesive layer, a second adhesive layer, and a heat sink element. The encapsulation layer fills a gap between a plurality of electrically conductive lines of the electrically conductive line pattern layer. An upper surface of the encapsulation layer is flush with an upper surface of the electrically conductive line pattern layer. The first and second adhesive layer are disposed between the electrically conductive line pattern layer and the heat sink element. A bonding strength between the first adhesive layer and the second adhesive layer is greater than 80 kg/cm.sup.2.

Implementations of semiconductor packages may include a metallic baseplate, a first insulative layer coupled to the metallic baseplate, a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the electrically insulative, one or more semiconductor devices coupled to each one of the first plurality of metallic traces, a second plurality of metallic traces coupled to the one or more semiconductor devices, and a second insulative layer coupled to the metallic traces of the second plurality of metallic traces.

A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver.

It is an object of the present invention to provide a semiconductor module that reduces an excessive stress on a sealed object due to the expansion and contraction of a sealing gel to thus improve the reliability. A semiconductor module according to the present invention includes: a semiconductor element bonded to a metal pattern on an insulating substrate contained in a case; a sealing gel sealing the insulating substrate and the semiconductor element within the case; and a sealing-gel-expansion suppressing plate disposed in the upper portion of the sealing gel to be at least partially in contact with the sealing gel. The sealing-gel-expansion suppressing plate includes a surface facing the sealing gel and inclined to the upper surface of the sealing gel.

Two conductive reference layers are embedded in a semiconductor package substrate. The embedded reference layers facilitate low electromagnetic noise coupling between adjacent signals for semiconductor device package.

A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.

A power module providing a half bridge comprises at least one substrate and an inner metallization area, two intermediate metallization areas and two outer metallization areas, each of which extends in a longitudinal direction of the at least one substrate; wherein the two intermediate metallization areas are arranged besides the inner metallization area with respect to a cross direction of the at least one substrate and each outer metallization area is arranged beside one of the two intermediate metallization areas with respect to the cross direction; wherein the power module comprises two inner sets of semiconductor switches, each inner set of semiconductor switches bonded to an intermediate metallization area and electrically connected to the inner metallization area, such that the inner sets of semiconductor switches form a first arm of the half bridge; wherein the power module comprises two outer sets of semiconductor switches, each outer set of semiconductor switches bonded to an outer metallization area and electrically connected to an intermediate metallization area, such that the outer sets of semiconductor switches form a second arm of the half bridge.