Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.

A prepreg contains a base material containing a reinforcing fiber and a semi-cured product of a resin composition impregnated into the base material containing a reinforcing fiber. The prepreg after cured has a glass transition temperature (Tg) which is higher than or equal to 150° C. and lower than or equal to 220° C. The resin composition contains (A) a thermosetting resin and (B) at least one compound selected from a group consisting of core shell rubber and a polymer component having a weight average molecular weight of 100000 or more. An amount of the (B) component is higher than or equal to 30 parts by mass and lower than or equal to 100 parts by mass with respect to 100 parts by mass of the (A) component.

A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the semiconductor chip and the dummy chip in the direction perpendicular to the first surface of the substrate, an upper end of the extension portion being disposed to be lower than the upper surface of the semiconductor chip; and a sealing material disposed on the first surface of the substrate, and sealing the semiconductor chip and the dummy chip.

An integrated circuit package may be formed comprising a substrate that includes a mold material layer and a signal routing layer, wherein the mold material layer comprises at least one bridge and at least one foam structure embedded in a mold material. In one embodiment, the substrate may include the mold material of the mold material layer filling at least a portion of cells within the foam structure. In a further embodiment, at least two integrated circuit devices may be attached to the substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.

An electronic device includes a substrate, an electronic component, a first interposing layer and a second interposing layer. The substrate is non-planar and the substrate includes a first substrate pad and a second substrate pad. The electronic component includes a first component pad and a second component pad corresponding to the first substrate pad and the second substrate pad respectively. When the first component pad contacts the first substrate pad, a height difference exists between the second component pad and the second substrate pad. The first interposing layer connects between the first component pad and the first substrate pad. The second interposing layer connects between the second component pad and the second substrate pad. A thickness difference between the first interposing layer and the second interposing layer is 0.5 to 1 time the height difference.

A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.

A substrate intermediary body includes: a substrate having a hole in a thickness direction, and a conductor being disposed in the hole; and an adhesion layer formed on a wall surface of the hole. The adhesion layer contains a reaction product of a polymer (A) having a cationic functional group and having a weight-average molecular weight of from 2,000 to 1,000,000 and a polyvalent carboxylic acid compound (B) having two or more carboxyl groups per molecule or a derivative thereof.

A semiconductor package includes a lower redistribution layer including an insulating pattern having an opening and a via in the opening; a first semiconductor chip including a chip pad, a passivation layer, and a pad bump connected to the chip pad; and a first encapsulant on the lower redistribution layer and the first semiconductor chip. The opening defines a lower surface and a side surface of the pad bump, and the via is in physical contact with the lower surface and the side surface of the pad bump.

There is provided a manufacturing method for an insulating resin circuit substrate, which is a manufacturing method for an insulating resin circuit substrate which includes an insulating resin layer composed of a polyimide resin and a circuit layer consisting of metal pieces disposed in a circuit pattern shape on one surface of the insulating resin layer. The manufacturing method includes a temporary fixing step of pressurizing the metal pieces toward the resin sheet material while heating the metal pieces to temporarily fix the metal pieces and a joining step of disposing a cushion material on a side of the metal pieces which are temporarily fixed and pressurizing the metal pieces and the resin sheet material in a laminating direction, while heating the metal pieces and the resin sheet material, to join the resin sheet material and the metal pieces.

Disclosed is a method for manufacturing a wiring structure including a step of forming a wiring on an insulating resin layer. The step of forming the wiring includes: forming a modified region including pores in a surface layer of the insulating resin layer by treating a surface of the insulating resin layer with a treatment method including surface modification; forming a seed layer on the surface of the insulating resin layer by sputtering; and forming the wiring on the seed layer by electrolytic copper plating. The disclosed method may include, in this order: a step of forming a surface treatment agent layer that covers a surface of the wiring by treating the surface of the wiring with a surface treatment agent for improving adhesion; and a step of forming a modified region including pores in a surface layer of a first layer of the insulating resin layer by treating the surface of the first layer of the insulating resin layer with a treatment method including surface modification.