A structure may include a first material, a second material joined to the first material at a junction between the first and second materials, and one or more media extending across the junction to form a continuous interconnect between the first and second materials, wherein the first and second materials are heterogeneous. The structure may further include a transition at the junction between the first and second materials. The one or more media may include a functional material which may be electrically conductive. The structure may further include a third material joined to the second material at a second junction between the second and third materials, the media may extend across the second junction to form a continuous interconnect between the first, second, and third materials, and the second and third materials may be heterogeneous.

A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.

An integrated circuit includes a semiconductor substrate, contact pads, testing pads, conductive posts, and dummy posts. The contact pads and the testing pads are distributed over the semiconductor substrate. The conductive posts are disposed on the contact pads. The dummy posts are disposed on the testing pads. A height of the conductive posts is greater than a height of the dummy posts.

At least some embodiments of the present disclosure relate to a wiring structure and a method for manufacturing a wiring structure. The wiring structure includes a conductive structure, a first fan-out structure, and a second fan-out structure. The first fan-out structure is disposed on the conductive structure and includes a first circuit layer. The second fan-out structure is disposed on the conductive structure, and includes a second circuit layer. A thickness of the first circuit layer is different from a thickness of the second circuit layer.

A method of manufacturing package structure with following steps is disclosed herein. An insulating composite layer is formed on a metal layer of a carrier board. A chip packaging module including a sealant and a first chip embedded therein is disposed on the insulating composite layer, in which the first chip has a plurality of conductive pads. A first circuit layer module including a dielectric layer and a circuit layer is formed on the chip packaging module, in which the circuit layer is on the dielectric layer and electrically connected to the conductive pads through a conductive vias in the dielectric layer. A second chip is disposed on the first circuit layer module. A second circuit layer module is formed on the first circuit layer module and the second chip. A protecting layer is formed on the second circuit layer module.

A semiconductor package includes a base film, a semiconductor die on the base film, metal studs on the semiconductor die, shielding pillars on the base film and around the semiconductor die, a first molding compound encapsulating the semiconductor die, the metal studs, and the shielding pillars, a first re-distribution structure on the first molding compound, a second molding compound on the first re-distribution structure, through-mold-vias in the second molding compound, and a second re-distribution structure on the second molding compound and electrically connected to the through-mold-vias. The second re-distribution structure comprises an antenna.

In a case of a multilayer wiring structure in which an insulating layer provided between wires is made of a material having high transmittance of light in a visible range containing ultraviolet rays, wires in the upper layer and those in a lower layer may be recognized together when defects of an upper layer are visually inspected. In this case, the lower layer may be noise for the inspection of the wires in the upper layer, lowering inspection accuracy. This lowered inspection accuracy has inhibited improvement in manufacturing yields and reliability. In order to solve this issue, a multilayer wiring substrate of the disclosure includes: a substrate; and a first wire and a second wire that are provided on the substrate with an insulating layer having a light transmitting property in between, and one or both of which are subjected to a surface treatment.

A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.

A method for forming an electronic chip assembly. A first metal plate is coupled to a first side of a substrate to form a backing plate. A first cavity is created extending through the substrate to extend at least to the first metal plate. An electronic component is bonded to the substrate such that the electronic component is located within the first cavity. A second metal plate, having a second cavity, is disposed to a second side of the substrate, and over the first cavity such that the electronic component is encased within the first and second cavities by the first and second metal plates.

A semiconductor package including a redistribution substrate with a first insulating layer, one or more second insulating layers on the first insulating layer, and a plurality of redistribution layers. The first insulating layer includes a first photosensitive resin having an elongation of 60% or more and toughness of 70 mJ/mm.sup.3 or more. The one or more second insulating layers include a second photosensitive resin having an elongation in a range of 10% to 40% and toughness of 40 mJ/mm.sup.3.