Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

A semiconductor package is disclosed. The semiconductor package may include a first redistribution substrate including a first insulating layer and a first redistribution pattern, a lower semiconductor chip mounted on the first redistribution substrate, a conductive structure disposed on the first redistribution substrate and horizontally spaced apart from the lower semiconductor chip, a first mold layer interposed between the first redistribution substrate and the second redistribution substrate to cover the lower semiconductor chip and the conductive structure, a second redistribution substrate on the first redistribution substrate, the second redistribution substrate including a second insulating layer and a second redistribution pattern, a first heat-dissipation pattern interposed between the lower semiconductor chip and the second insulating layer, and a heat-dissipation pad on the conductive structure. A top surface of the first heat-dissipation pattern may be located at a level higher than a top surface of the conductive structure.

Techniques are described herein for a reconfigurable memory device that is configurable based on the type of interposer used to couple the memory device with a host device. The reconfigurable memory device may include a plurality components for a plurality of configurations. Various components of the reconfigurable memory die may be activated/deactivated based on what type of interposer is used in the memory device. For example, if a first type of interposer is used (e.g., a high-density interposer), the data channel may be eight data pins wide. In contrast, if second type of interposer is used (e.g., an organic-based interposer), the data channel may be four data pins wide. As such, a reconfigurable memory device may include data pins and related drivers that are inactive in some configurations.

A device includes an interconnect device attached to a redistribution structure, wherein the interconnect device includes conductive routing connected to conductive connectors disposed on a first side of the interconnect device, a molding material at least laterally surrounding the interconnect device, a metallization pattern over the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the conductive connectors, first external connectors connected to the metallization pattern, and semiconductor devices connected to the first external connectors.

An integrated fan out package is utilized in which the dielectric materials of different redistribution layers are utilized to integrate the integrated fan out package process flows with other package applications. In some embodiments an Ajinomoto or prepreg material is utilized as the dielectric in at least some of the overlying redistribution layers.

Disclosed herein are waveguide interconnect bridges for integrated circuit (IC) structures, as well as related methods and devices. In some embodiments, a waveguide interconnect bridge may include a waveguide material and one or more wall cavities in the waveguide material. The waveguide interconnect bridge may communicatively couple two dies in an IC package.

A semiconductor package including a semiconductor die, an encapsulant, an electrical connector, a conductive pad and an inter-dielectric layer is provided. The encapsulant encapsulates the semiconductor die. The electrical connector is disposed over the semiconductor die. The conductive pad contacts the electrical connector and is disposed between the semiconductor die and the electrical connector. The inter-dielectric layer is disposed over the semiconductor die, wherein the inter-dielectric layer comprises an opening, and a portion of the opening is occupied by the conductive pad and the electrical connector.

Package structure and method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a third die, and a second encapsulant. The first die and the second die laterally aside the first die. The first encapsulant laterally encapsulates the first die and the second die. The third die is electrically connected to the first die and the second die. The second encapsulant is over the first die, the second die and the first encapsulant, laterally encapsulating the third die. The first encapsulant includes a plurality of first fillers, the second encapsulant includes a plurality of second fillers, and a content of the second fillers in the second encapsulant is less than a content of the first fillers in the first encapsulant.

A device includes an interconnect device attached to a redistribution structure, wherein the interconnect device includes conductive routing connected to conductive connectors disposed on a first side of the interconnect device, a molding material at least laterally surrounding the interconnect device, a metallization pattern over the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the conductive connectors, first external connectors connected to the metallization pattern, and semiconductor devices connected to the first external connectors.

An integrated circuit comprises a substrate including a shape memory polymer, and a semiconductor die mounted on the substrate.