Composite IC die package including IC die on both a first and second side of an interposer. The backside of first IC die are attached, for example through a direct bond, to a first side of the interposer. Redistribution layer (RDL) metal features are then fabricated, for example with semi-additive processes (SAP), to form interconnects to the frontside of the first die that terminate at first-level interconnect (FLI) interfaces. The frontside of second IC are attached, for example through a direct bond, to a second side of the interposer. Through vias in the interposer couple the second IC die to the first IC die and/or the FLI interfaces. Through vias of the interposer may be coupled to pillars on the first side of the interposer with the first IC die positioned between the pillars, facilitating power delivery to the second IC die.

A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.

A method of forming an interposer includes providing a first interposer substrate including a first bulk material having a plurality of first through silicon vias (TSVs) extending through the first bulk material. A second interposer substrate is provided and includes a second bulk material having a plurality of second TSVs extending through the second bulk material, and a wiring plane formed on the second bulk material such that the wiring plane is electrically connected to at least one of the second TSVs. The method further includes joining the first interposer substrate to the second interposer substrate such that the wiring plane is provided as an interface wiring plane between the first and second bulk materials which electrically connects at least one of the first TSVs to at least one of the second TSVs.

In an aspect, a heterojunction bipolar transistor (HBT) includes a sub-collector disposed on a collector. The collector has a collector contact disposed on the sub-collector and located on a first side of the heterojunction bipolar transistor. The HBT includes an emitter disposed on an emitter cap. The emitter has an emitter contact disposed on the emitter cap and located on a second side of the heterojunction bipolar transistor. The HBT includes a base having a base contact located on the second side of the heterojunction bipolar transistor.

A semiconductor device includes a first plurality of dies on a wafer, a first redistribution structure over the first plurality of dies, and a second plurality of dies on the first redistribution structure opposite the first plurality of dies. The first redistribution structure includes a first plurality of conductive features. Each die of the first plurality of dies are bonded to respective conductive features of the first plurality of conductive features by metal-metal bonds on a bottom side of the first redistribution structure. Each die of the second plurality of dies are bonded to respective conductive features of the first plurality of conductive features in the first redistribution structure by metal-metal bonds on a top side of the first redistribution structure.

A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

A quantum device according to an example embodiment includes: a quantum chip with a first surface and a second surface located on a side opposite to the first surface, in the quantum chip, at least a part of a qubit circuit being provided on the second surface; a first interposer with a third surface and a fourth surface located on a side opposite to the third surface, the first interposer being connected to the quantum chip in such a manner that the second surface of the quantum chip is opposed to the third surface of the first interposer; and a second interposer with a fifth surface and a sixth surface located on a side opposite to the fifth surface, the second interposer being connected to the first interposer in such a manner that the fourth surface of the first interpose is opposed to the fifth surface of the second interposer.

A package comprises an interposer, comprising an interposer substrate including at least one layer, and a plurality of RDLs formed through at least a portion of the interposer substrate. The package also includes a die device structure comprising at least one device die, and a first test line (TL) structure interposed between the interposer and the die device structure. The first TL structure includes at least one first test line electrically coupled to the at least one device die, at least a portion of the at least one first test line extending beyond a peripheral edge of the die device structure to provide an electrical interface with the at least one device die.

A method of fabricating a semiconductor package includes disposing a preliminary semiconductor package on a stage, the preliminary semiconductor package including a substrate to which a pad part is attached, an interposer disposed on the substrate, and a semiconductor chip disposed between the substrate and the interposer. A bonding tool is disposed on the interposer. The bonding tool includes a first region and a second region outside of the first region. The second region of the bonding tool corresponds to the pad part. The interposer and the substrate are bonded to each other.