A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

An electrical component is provided by metallizing holes that extend through a glass substrate. The electrical component can be fabricated by forcing a suspension of electrically conductive particles suspended in a liquid medium through the holes. The suspension can be forced into the holes under an air pressure differential such as a pressure differential force, a centrifugal force, or an electrostatic force. The liquid medium in the holes can be dried, and the particles can be sintered. The particles can further be packed in the hole. Alternatively or additionally, the particles can be pressed against the outer surfaces of the substrate to produce buttons.

An electrical component is provided by metallizing holes that extend through a glass substrate. The electrical component can be fabricated by forcing a suspension of electrically conductive particles suspended in a liquid medium through the holes. The suspension can be forced into the holes under an air pressure differential such as a pressure differential force, a centrifugal force, or an electrostatic force. The liquid medium in the holes can be dried, and the particles can be sintered. The particles can further be packed in the hole. Alternatively or additionally, the particles can be pressed against the outer surfaces of the substrate to produce buttons.

A method of producing a glass substrate having a hole is provided. The method includes preparing the glass substrate having a first surface and a second surface facing each other; forming a hole in the glass substrate with a laser; and annealing the glass substrate placed on a first support substrate having a thermal expansion coefficient whose difference from a thermal expansion coefficient of the glass substrate is less than or equal to 1 ppm/K, where the first support substrate is placed on a second support substrate having a thermal expansion coefficient of less than or equal to 10 ppm/K.

One aspect of the present invention provides a composite sheet which comprises a nitride sintered body having a porous structure and a semi-cured product of a thermosetting resin composition impregnated into the nitride sintered body, the line roughness Rz specified by JIS B 0601:2013 of at least one main surface being 10 μm or less.

Embodiments described herein may be related to apparatuses, processes, and techniques related to forming capacitors using lines in a bond pad layer within hybrid bonding techniques of two separate dies and then coupling those dies. In embodiments, these techniques may involve using dummy bond pads, where the width of these dummy bond pads are smaller than that of active bond pads, to create a pattern to serve as a capacitor structure. Other embodiments may be described and/or claimed.

Embodiments described herein may be related to apparatuses, processes, and techniques related to positioning signal and ground vias, or ground planes, in a glass core to control impedance within a package. Laser-assisted etching processes may be used to create vertical controlled impedance lines to enhance bandwidth and bandwidth density of high-speed signals on a package. Other embodiments may be described and/or claimed.

Embodiments described herein may be related to apparatuses, processes, and techniques related to positioning signal and ground vias, or ground planes, in a glass core to control impedance within a package. Laser-assisted etching processes may be used to create vertical controlled impedance lines to enhance bandwidth and bandwidth density of high-speed signals on a package. Other embodiments may be described and/or claimed.

Embodiments disclosed herein include package substrates with angled vias and/or via planes. In an embodiment, a package substrate comprises a core with a first surface and a second surface opposite from the first surface. In an embodiment, a first pad is on the first surface, and a second pad on the second surface, where the second pad is outside a footprint of the first pad. In an embodiment, the package substrate further comprises a via through a thickness of the core, where the via connects the first pad to the second pad.

Embodiments disclosed herein include package substrates with angled vias and/or via planes. In an embodiment, a package substrate comprises a core with a first surface and a second surface opposite from the first surface. In an embodiment, a first pad is on the first surface, and a second pad on the second surface, where the second pad is outside a footprint of the first pad. In an embodiment, the package substrate further comprises a via through a thickness of the core, where the via connects the first pad to the second pad.