H01L23/20

ELECTRONIC DEVICE INCLUDING RIGID DIELECTRIC LID AND OVERLAYING THERMOSET POLYMER LAYER AND RELATED METHODS
20240203809 · 2024-06-20 ·

An electronic device may include a dielectric substrate and bond wire pads on an upper surface thereof. The electronic device may also include a radio frequency (RF) integrated circuit (IC) mounted to the upper surface of the dielectric substrate and bond wires coupling the RF IC to respective bond wire pads. The electronic device may also include a rigid dielectric lid mounted to the upper surface of the dielectric substrate to define an air cavity above the RF IC and the bond wires, and a thermosetting polymer layer over the rigid dielectric lid.

Integrated circuit packages to minimize stress on a semiconductor die

An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

Integrated circuit packages to minimize stress on a semiconductor die

An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

HERMETICALLY SEALED HOUSING WITH A SEMICONDUCTOR COMPONENT AND METHOD FOR MANUFACTURING THEREOF
20190131154 · 2019-05-02 ·

A method is provided for producing a hermetically sealed housing having a semiconductor component. The method comprises introducing a housing having a housing body and a housing cover into a process chamber. The housing cover closes off a cavity of the housing body and is attached in a gas-tight manner to the housing body. At least one opening is formed in the housing. At least one semiconductor component is arranged in the cavity. The method furthermore comprises generating a vacuum in the cavity by evacuating the process chamber, and also generating a predetermined gas atmosphere in the cavity and the process chamber. The method moreover comprises applying sealing material to the at least one opening while the predetermined gas atmosphere prevails in the process chamber.

Multi-level getter structure and encapsulation structure comprising such a multi-level getter structure

A getter structure is provided, including a support; a first layer of getter material disposed on the support a second layer of getter material, the first layer of getter material being disposed between the support and the second layer of getter material; a first portion of material mechanically connecting a first face of the second layer of getter material to a first face of the first layer of getter material and forming at least one first space between the first faces of the first and second layers of getter material configured to allow a circulation of gas between the first faces of the first and second layers of getter material; and a first opening crossing through at least the second layer of getter material and emerging into the first space.

Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer

A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned integrated passive die (IPD) attached to the printed circuit substrate. A protective layer is disposed over the thinned IPD to protect passive devices integrated within the thinned IPD, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 10.sup.3 Ohm-cm.

Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer

A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned integrated passive die (IPD) attached to the printed circuit substrate. A protective layer is disposed over the thinned IPD to protect passive devices integrated within the thinned IPD, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 10.sup.3 Ohm-cm.

Device Package with Reduced Radio Frequency Losses

A device package includes a semiconductor device. The semiconductor device is disposed on a substrate. The device package further includes a covering. The covering is disposed on the substrate and surrounds the semiconductor device. The covering includes a void, a first layer, and a second layer. The void is between an interior surface of the covering and the semiconductor device. The first layer has a first electrical conductivity and a first thickness. The second layer is disposed under the first layer. The second layer has a second electrical conductivity and a second thickness. The first electrical conductivity is greater than the second electrical conductivity. The first thickness is less than the second thickness.

Remapped packaged extracted die with 3D printed bond connections

An integrated circuit is provided. The integrated circuit includes a package base including package leads, an extracted die removed from a previous packaged integrated circuit, and an an interposer bonded to the extracted die and the package base. The extracted die includes original bond pads and one or more original ball bonds on the original bond pads. The interposer includes first bond pads electrically connected to the original bond pads with 3D printed first bond connections conforming to the shapes and surfaces of the extracted die and the interposer and second bond pads electrically connected to the package leads with 3D printed second bond connections conforming to shapes and surfaces of the interposer and package base.

Remapped packaged extracted die with 3D printed bond connections

An integrated circuit is provided. The integrated circuit includes a package base including package leads, an extracted die removed from a previous packaged integrated circuit, and an an interposer bonded to the extracted die and the package base. The extracted die includes original bond pads and one or more original ball bonds on the original bond pads. The interposer includes first bond pads electrically connected to the original bond pads with 3D printed first bond connections conforming to the shapes and surfaces of the extracted die and the interposer and second bond pads electrically connected to the package leads with 3D printed second bond connections conforming to shapes and surfaces of the interposer and package base.