An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. An opening in the encapsulation extends from the encapsulation top surface to a conductive feature on the top surface of the component. A conductive termination structure within the encapsulation opening extends from the conductive feature to the encapsulation top surface. The device also may include a second circuit physically coupled to the encapsulation top surface and electrically coupled to the component through the conductive termination structure. In an alternate embodiment, the conductive termination structure may be located in a trench in the encapsulation that extends between two circuits that are embedded within the encapsulation, where the conductive termination structure is configured to reduce electromagnetic coupling between the two circuits during device operation.

A 2-in-1 power electronics assembly includes a frame with a lower dielectric layer, an upper dielectric layer spaced apart from the lower dielectric layer, and a sidewall disposed between and coupled to the lower dielectric layer and the upper dielectric layer. The lower dielectric layer includes a lower cooling fluid inlet and the upper dielectric layer includes an upper cooling fluid outlet. A first semiconductor device assembly and a second semiconductor device assembly are included and disposed within the frame. The first semiconductor device is disposed between a first lower metal inverse opal (MIO) layer and a first upper MIO layer, and the second semiconductor device is disposed between a second lower MIO layer and a second upper MIO layer. An internal cooling structure that includes the MIO layers provides double sided cooling for the first semiconductor device and the second semiconductor device.

In one aspect, a liquid-based encapsulation system includes an electronic material having a plurality of exposed surfaces; and an encapsulating liquid disposed over an entirety of the exposed surfaces of the electronic material to prevent diffusion of water past the encapsulating liquid and to protect the electronic material from water. In one aspect, a method of making a liquid-based encapsulation system includes providing an electronic material having a plurality of exposed surfaces; and encapsulating the electronic material with an encapsulating liquid over an entirety of the exposed surfaces of the electronic material to prevent diffusion of water past the encapsulating liquid and to protect the electronic material from water.

In one aspect, a liquid-based encapsulation system includes an electronic material having a plurality of exposed surfaces; and an encapsulating liquid disposed over an entirety of the exposed surfaces of the electronic material to prevent diffusion of water past the encapsulating liquid and to protect the electronic material from water. In one aspect, a method of making a liquid-based encapsulation system includes providing an electronic material having a plurality of exposed surfaces; and encapsulating the electronic material with an encapsulating liquid over an entirety of the exposed surfaces of the electronic material to prevent diffusion of water past the encapsulating liquid and to protect the electronic material from water.

A fan-out semiconductor package includes: a semiconductor chip having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the active surface of the semiconductor chip, wherein the encapsulant is a cured photosensitive resin composition including a thermosetting resin, a carboxylic resin, an ethylenically unsaturated compound, and a reinforcing agent. The photosensitive resin composition may be used in the fan-out semiconductor package.

The present disclosure discloses an electroluminescent display and the encapsulation method thereof. The electroluminescent display comprises: a substrate having encapsulation units provided on a side surface of the substrate; a cover plate covering the substrate, wherein the cover plate together with the encapsulation units defines a first chamber and a second chamber, the second chamber surrounds the first chamber; an electronic device provided on the substrate and located within the first chamber, wherein the first chamber is filled with inert gas and the second chamber is filled with a hydrophobic liquid. The electroluminescent display according to an embodiment of the present disclosure can prevent water vapor and oxygen from entering the electronic device. The entire system has a good sealing performance, such that a service life of the electronic device can be greatly extended.

Chip packages and electronic devices are provided that include a thermal capacitance element that improves the operation of IC dies at elevated temperatures. In one example, a chip package is provided that includes an integrated circuit (IC) die, a lid thermally connected to the IC die, and a thermal capacitance element thermally connected to the lid. The thermal capacitance element includes a container and a capacitance material sealingly disposed in the container. The capacitance material has a phase transition temperature that is between 80 and 100 percent of a maximum designed operating temperature in degrees Celsius of the IC die.

A semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an upper portion of the first semiconductor chip, a second semiconductor chip on an upper surface of the first semiconductor chip and being electrically connected to the first semiconductor chip through the through silicon via of the first semiconductor chip, and an insulating bonding layer between the first semiconductor chip and the second semiconductor chip. The insulating bonding layer fills the first trench portion.

An antenna device includes a radio frequency (RF) die, a first dielectric layer, a feeding line, a ground line, a second dielectric layer, and a radiating element. The first dielectric layer is over the RF die. The feeding line is in the first dielectric layer and is connected to the RF die. The ground line is in the first dielectric layer and is spaced apart from the feeding line. The second dielectric layer covers the first dielectric layer. The radiating element is over the second dielectric layer and is not in physically contact with the feeding line.

Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.