Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.

A relay substrate in which a circuit pattern and an external electrode are integrated on a insulating plate is used in the semiconductor device. Such configuration makes it possible to reduce a resistance in a current path while preventing the problems occurring when the external electrode is soldered on the semiconductor chip.

A semiconductor device package includes a substrate having first and second opposing surfaces. A first surface of a die couples to the second surface of the substrate, and a first surface of an electrically conductive sub-terminal electrically couples with an electrical contact of the die and physically couples to the second surface of the substrate. A mold compound encapsulates the die and a majority of the sub-terminal. In implementations a first surface of the mold compound is coupled to the second surface of the substrate and a second surface of the mold compound opposing the first surface of the mold compound is flush with a second surface of the sub-terminal opposing the first surface of the sub-terminal. In implementations the sub-terminal includes a pillar having a longest length perpendicular to a longest length of the substrate. In implementations an electrically conductive pin couples to the second surface of the sub-terminal.

A semiconductor device package includes a substrate having first and second opposing surfaces. A first surface of a die couples to the second surface of the substrate, and a first surface of an electrically conductive sub-terminal electrically couples with an electrical contact of the die and physically couples to the second surface of the substrate. A mold compound encapsulates the die and a majority of the sub-terminal. In implementations a first surface of the mold compound is coupled to the second surface of the substrate and a second surface of the mold compound opposing the first surface of the mold compound is flush with a second surface of the sub-terminal opposing the first surface of the sub-terminal. In implementations the sub-terminal includes a pillar having a longest length perpendicular to a longest length of the substrate. In implementations an electrically conductive pin couples to the second surface of the sub-terminal.

A method of manufacturing a semiconductor device, including preparing a heat-dissipating base, performing a first initial warping or a second initial warping of the heat-dissipating base, soldering a laminated substrate, including a circuit board provided on an insulating board, on the heat-dissipating base after the first or second initial warping, and soldering a semiconductor chip on the circuit board. The first initial warping includes performing shot peening on the rear surface of the heat-dissipating base to form a hardened layer, and subsequently plating the front and rear surfaces of the heat-dissipating base, including the hardened layer formed thereon, with a metal material. The second initial warping includes plating the front and rear surfaces of the heat-dissipating base with the metal material to form a plating layer, and subsequently performing the shot peening on the rear surface of the heat-dissipating base, including the plating layer formed thereon, with the metal material.

A method of manufacturing a semiconductor device, including preparing a heat-dissipating base, performing a first initial warping or a second initial warping of the heat-dissipating base, soldering a laminated substrate, including a circuit board provided on an insulating board, on the heat-dissipating base after the first or second initial warping, and soldering a semiconductor chip on the circuit board. The first initial warping includes performing shot peening on the rear surface of the heat-dissipating base to form a hardened layer, and subsequently plating the front and rear surfaces of the heat-dissipating base, including the hardened layer formed thereon, with a metal material. The second initial warping includes plating the front and rear surfaces of the heat-dissipating base with the metal material to form a plating layer, and subsequently performing the shot peening on the rear surface of the heat-dissipating base, including the plating layer formed thereon, with the metal material.

A semiconductor sensor device is assembled using a lead frame having a flag surrounded by lead fingers. A pressure sensor die is mounted on the flag and electrically connected to the leads. Prior to encapsulation, a pre-formed block of gel material is placed over the sensor region on the die. Encapsulation is performed and mold compound covers the pressure sensor die and the bond wires. Mold compound covering the gel block may be removed. Additionally, a trench may be formed around an upper portion of the gel block so that the lateral sides of the gel block are at least partially exposed.

A semiconductor package and a manufacturing method thereof are disclosed. The semiconductor package includes a device carrier and a stiffener structure. The device carrier includes at least one insulating layer and at least conductive layer defining at least one trace layout unit. The stiffener structure is disposed on the device carrier, surrounding the periphery of the at least one trace layout unit. The stiffener structure is disposed away from the periphery of the at least one trace layout unit, forming a cavity with the device carrier. The shape and disposition of the stiffener structure enhance the strength of the semiconductor package, impeding flexure to the semiconductor package.

A semiconductor package and a manufacturing method thereof are disclosed. The semiconductor package includes a device carrier and a stiffener structure. The device carrier includes at least one insulating layer and at least conductive layer defining at least one trace layout unit. The stiffener structure is disposed on the device carrier, surrounding the periphery of the at least one trace layout unit. The stiffener structure is disposed away from the periphery of the at least one trace layout unit, forming a cavity with the device carrier. The shape and disposition of the stiffener structure enhance the strength of the semiconductor package, impeding flexure to the semiconductor package.

A metal member includes a plate-shaped portion provided on an upper main surface of a substrate, and includes a front main surface and a back main surface arranged in a front-back direction when viewed in an up-down direction. A first electronic component is mounted on the upper main surface of the substrate and is disposed in front of the metal member. A second electronic component is mounted on the upper main surface of the substrate and is disposed behind the metal member. A sealing resin layer is provided on the upper main surface of the substrate and covers the metal member and the one or more electronic components. The plate-shaped portion is provided with one or more upper notches extending downward from the upper side. The metal member further includes one or more foot portions extending forward or backward from the lower side.