Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.

Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.

A semiconductor device includes a metal plate; a sidewall member surrounding a periphery of a space above the metal plate; a circuit board provided on the metal plate; a semiconductor chip provided on the circuit board; a first wire connecting the semiconductor chip and an interconnect part of the circuit board; a first resin member covering a bonding portion between the semiconductor chip and the first wire; and a second resin member provided in the space, the second resin member covering an upper surface of the metal plate, the circuit board, the first resin member, and the first wire. A Young's modulus of the first resin member is greater than a Young's modulus of the second resin member. A volume of the second resin member is greater than a volume of the first resin member.

Methods and apparatus are disclosed to provide electrical shielding for integrated circuit packages using a thermal interface material. An integrated circuit package includes a substrate including a ground plane layer and a solder mask; a semiconductor die attached to the substrate, the solder mask layer separating the semiconductor die from the ground plane layer; and a thermal interface material surrounding at least a portion of the semiconductor die, the thermal interface material electrically coupled to the ground plane layer.

A semiconductor device includes first, second, and third metal layers on a surface of the insulating substrate. A first terminal is connected to the first metal layer at a first region. A second terminal is connected to the second metal layer at a second region. An output terminal is connected to the third metal layer. First chips are aligned along a first direction on the first metal layer. Second chips are aligned along the first direction on the third metal layer. A first wire connects a first upper electrode of a first chip to the third metal layer. A second wire connects a second upper electrode of a second chip to the second metal layer. The second chips are between the first chips and the third metal layer in a second direction perpendicular to the first direction. Available conductive routes between the first and second terminals are made more uniform.

We herein describe a semiconductor device sub-assembly comprising at least two power semiconductor devices and a contact of a first type. A first power semiconductor device is located on a first side of the contact of a first type, and a second power semiconductor device is located on a second side of the contact of a first type, where the second side is opposite to the first side.

A semiconductor device includes a package substrate, and a first die group bonded onto the package substrate. The first die group characterized by a first thickness. The semiconductor device also has a second die group bonded onto the package substrate. The second die group characterized by a second thickness. The semiconductor device further includes a carrier substrate disposed on the first die group. The carrier substrate is characterized by a third thickness that is a function of a difference between the first thickness and the second thickness. A molding compound material is disposed on the package substrate and covers the first die group and the second die group. The molding compound material includes a cavity between the first die group and the second die group.

A semiconductor device includes a package substrate, and a first die group bonded onto the package substrate. The first die group characterized by a first thickness. The semiconductor device also has a second die group bonded onto the package substrate. The second die group characterized by a second thickness. The semiconductor device further includes a carrier substrate disposed on the first die group. The carrier substrate is characterized by a third thickness that is a function of a difference between the first thickness and the second thickness. A molding compound material is disposed on the package substrate and covers the first die group and the second die group. The molding compound material includes a cavity between the first die group and the second die group.

A semiconductor chip includes semiconductor dice contained in a packaging apparatus including a cover and a plate, thereby forming a vapor chamber. The semiconductor dice and intermediate layers are alternately stacked. A capillary mechanism is provided on a horizontal internal face of the cover. Nets are provided on vertical internal faces of the cover, around the capillary mechanism. Each of the intermediate layers includes protuberances in contact with the nets. A channel is defined between any adjacent two of the protuberances. The channels travel past the intermediate layers. Coolant filled in the vapor chamber is turned into vapor after absorbing heat. The vapor ascends to the cover via the channels. The coolant is returned into liquid after transferring heat to the cover. The liquid descends to the plate. Thus, the coolant is circulated in the vapor chamber. Each of the intermediate layers includes a capillary structure to facilitate the circulation of the coolant.

A resin enclosure includes: an inner wall portion from a wall surface defining the space to a side surface of the lead terminal close to the space; and a covering portion that covers at least a part of a top surface of a first portion of the lead terminal.