A semiconductor module includes a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a reinforcing structure contained within the interior volume and including a textured surface that is accessible by fluid, a volume of curable encapsulant disposed within the interior volume and encapsulating the power semiconductor die, wherein the reinforcing structure is embedded within the volume of curable encapsulant such that the textured surface adheres to the encapsulant, and wherein the reinforcing structure has a tensile strength that is greater than a tensile strength of the curable encapsulant.

A semiconductor module includes a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a reinforcing structure contained within the interior volume and including a textured surface that is accessible by fluid, a volume of curable encapsulant disposed within the interior volume and encapsulating the power semiconductor die, wherein the reinforcing structure is embedded within the volume of curable encapsulant such that the textured surface adheres to the encapsulant, and wherein the reinforcing structure has a tensile strength that is greater than a tensile strength of the curable encapsulant.

An electrical component and method for manufacturing the electrical component with a substrate a conductor stack having multiple layers and including at least one electrically conductive path. The conductor stack mounted to the substrate with a dielectric passivation stack encasing at least a portion of the conductor stack.

An electrical component and method for manufacturing the electrical component with a substrate a conductor stack having multiple layers and including at least one electrically conductive path. The conductor stack mounted to the substrate with a dielectric passivation stack encasing at least a portion of the conductor stack.

A bonded structure is disclosed. The bonded structure can include a first element that has a first bonding surface. The bonded structure can further include a second element that has a second bonding surface. The first and second bonding surfaces are bonded to one another along a bonding interface. The bonded structure can also include an integrated device that is coupled to or formed with the first element or the second element. The bonded structure can further include a channel that is disposed along the bonding interface around the integrated device to define an effectively closed profile The bonded structure can also include a getter material that is disposed in the channel. The getter material is configured to reduce the diffusion of gas into an interior region of the bonded structure.

A bonded structure is disclosed. The bonded structure can include a first element that has a first bonding surface. The bonded structure can further include a second element that has a second bonding surface. The first and second bonding surfaces are bonded to one another along a bonding interface. The bonded structure can also include an integrated device that is coupled to or formed with the first element or the second element. The bonded structure can further include a channel that is disposed along the bonding interface around the integrated device to define an effectively closed profile The bonded structure can also include a getter material that is disposed in the channel. The getter material is configured to reduce the diffusion of gas into an interior region of the bonded structure.

Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.

Various semiconductor chips with gettering regions and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a first side and a second side opposite the first side. The first side has a plurality of laser ablation craters. Each of the ablation craters has a bottom. A gettering region is in the semiconductor chip beneath the laser ablation craters. The gettering region includes plural structural defects. At least some of the structural defects emanate from at least some of the bottoms of the laser ablation craters.

A hermetically sealed electronic package may include a thermal panel having a panel interior surface and a panel exterior surface with electronic device(s) in thermal communication with the panel interior surface. An enclosure, isolating environmental communication from internal electronic devices and modules, may be coupled to the thermal panel, and the enclosure may have an enclosure interior surface and an enclosure exterior surface. A plurality of electrical feedthroughs may be coupled to the package enclosure for signal and data transmission, and the conducting pin(s) in every electrical feedthrough may be bonded by a hydrophobic sealing material for harsh environmental electrical signal, data and power transmission. The ratio of sealing length over sealing bead diameter in the electrical feedthrough subassembly may have a preferred value from 2 to 3; and the ratio of the sealing bead diameter over pin diameter in the electrical feedthrough subassembly may have a preferred value from 1.5 to 2.0, where a preferred thermal stress resistance could be designed for making highly hermetic sealed electronic package.

The package comprises a carrier, an electronic device arranged on the carrier, a shield arranged on the electronic device on a side facing away from the carrier, and an absorber film comprising nanomaterial applied on or above the shield.