A reinforcing resin composition includes an epoxy resin (A), a phenolic resin (B), and a benzoxazine compound (C).

A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

An annular dielectric spacer can be formed at a level of a joint-level dielectric material layer between vertically neighboring pairs of alternating stacks of insulating layers and spacer material layers. After formation of a memory opening through multiple alternating stacks and formation of a memory film therein, an anisotropic etch can be performed to remove a horizontal bottom portion of the memory film. The annular dielectric spacer can protect underlying portions of the memory film during the anisotropic etch. In addition, a silicon nitride barrier may be employed to suppress hydrogen diffusion at an edge region of peripheral devices.

Disclosed is a semiconductor device that is configured to contain a sealing layer for sealing a semiconductor element supported on a base, the sealing layer being configured to have a nanocomposite structure that comprises a large number of nanometer-sized (1 μm or smaller) insulating nanoparticles composed of SiO.sub.2, and an amorphous silica matrix that fills up the space around the insulating nanoparticles without voids and gaps.

A method for depositing a dielectric layer that includes introducing a substrate into a process chamber of a deposition tool; and heating the substrate to a process temperature. The method may further include introducing precursors that include at least one dielectric providing gas species for a deposited layer and at least one hydrogen precursor gas into the process chamber of the deposition tool. The hydrogen precursor gas is introduced to the deposition chamber at a flow rate ranging from 50 sccm to 5000 sccm. The molar ratio for Hydrogen/Silicon gas precursor can be equal or greater than 0.05.

A method of manufacturing a high electron mobility transistor in a furnace, the method including steps of: forming a first SiN film on a surface of a semiconductor stack consisting of a nitride semiconductor and including a barrier layer by a low pressure chemical vapor deposition method at a first furnace temperature of 700° C. or more and 900° C. or less; forming an interface oxide layer on the first SiN film by moisture and oxygen in the furnace at a second furnace temperature of 700° C. or more and 900° C. or less and a furnace pressure to 1 Pa or lower; and forming a second SiN film on the interface oxide layer by the low pressure chemical vapor deposition method at a third furnace temperature of 700° C. or more and 900° C. or less.

This method concerns the protection against humidity of a device including a first and a second electronic components respectively having two opposite surfaces, the surfaces: being separated by a non-zero distance shorter than 10 micrometers; having an area greater than 100 mm.sup.2; being connected by an assembly of electrical interconnection elements spaced apart from one another by a space void of matter. This method includes applying a deposit of thin atomic layers onto the device to form a layer of mineral material covering at least the interconnection elements, the layer of mineral material having a permeability to water vapor smaller than or equal to 10.sup.−3 g/m.sup.2/day.

Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a trench in a substrate, the trench being formed within a first side of the substrate and disposed around a portion of the substrate. A first insulating material is formed over the first side of the substrate and the trench, and a second insulating material is formed over the first insulating material. Apertures are formed in the second insulating material and the first insulating material over the portion of the substrate. Features are formed in the apertures, and a carrier is coupled to the features and the second insulating material. A second side of the substrate is planarized, the second side of the substrate being opposite the first side of the substrate. The second insulating material is removed, and the carrier is removed.

A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.