A microelectronic package having an encapsulated substrate comprising a plurality of microelectronic devices encapsulated within an encapsulation material, wherein the encapsulated structure may have an active surface proximate the active surfaces of the plurality of microelectronic devices, and wherein at least one of the plurality of microelectronic devices may have a height greater than another of the plurality of microelectronic devices (e.g. non-coplanar). The microelectronic package further includes a bumpless build-up layer structure formed proximate the encapsulated structure active surface. The microelectronic package may also have an active surface microelectronic device positioned proximate the encapsulated structure active surface and in electrical contact with at least one of the plurality of microelectronic devices of the encapsulated substrate.

A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.

A semiconductor package includes an extendible molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. First surfaces of the connectors are exposed at a surface of the molding member, and second surfaces of the connectors are coupled to the chip.

The invention provides a fingerprint sensor package and a method for fabricating the same. The fingerprint sensor package includes a substrate. A first fingerprint sensor die is disposed on the substrate. A molding compound layer is disposed on the substrate, encapsulating the first fingerprint sensor die. Filler are dispersed in the molding compound layer. The diameter of the fillers is less than or about 20 m.

Techniques are disclosed for wafer bonding with an encapsulation layer. A first semiconductor substrate is provided. An encapsulation layer is then formed on top of the first semiconductor substrate. The encapsulation layer is formed of an encapsulation material that creates a stable oxide when exposed to an oxidizing agent. A first bonding layer is formed on top of the encapsulation layer. Next, a second semiconductor substrate is provided. A second bonding layer is formed on top of the second bonding layer. Thereafter, the first semiconductor substrate is bonded to the second semiconductor substrate by attaching the first bonding layer to the second bonding layer.

A tool and method for processing substrates by encapsulating a mask to protect from degradation during an etch-back to prevent a feature liner material from pinching off an opening during deposition-etch cycles used to fabricate high aspect ratio features with very tight critical dimension control.

The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height.

An electronic package and the manufacturing method thereof are provided. The method includes forming a circuit structure on an encapsulating structure with a recess and a plurality of vias, disposing a plurality of conductive pillars in the plurality of vias to be electrically connected to the circuit structure, and disposing an electronic component in the recess to be electrically connected to the circuit structure. Afterwards, a routing structure is disposed on the encapsulating structure to be electrically connected to the plurality of conductive pillars and the electronic component. Therefore, by disposing the electronic component in the recess, the encapsulating structure covers the electronic component to facilitate dissipation of thermal stress.

A stress-reduced silicon photonics semiconductor wafer includes a silicon nitride layer on a backside of the wafer. At least one silicon nitride stress-reduction configuration is on a topside of the wafer. At least one silicon nitride photonics device is also on the topside of the wafer. A silicon photonics device can be situated in the wafer.

A semiconductor package includes: a leadframe having first, second and third die pads and leads, each die pad having upper and lower surfaces; first and second power semiconductor devices; a control semiconductor device; and a mold compound. The upper surface of each die pad is arranged within the mold compound. The lower surface of the second die pad is spaced apart from a side face of the semiconductor package by a distance that is greater than a length of the individual leads. The first power semiconductor device is mounted on the upper surface of the first die pad and electrically coupled to the second die pad by one or more first connectors extending between the first device and the upper surface of the second die pad. The upper surface of the second die pad is occupied by the one or more connectors or in direct contact with the mold compound.