A method for encapsulating a microelectronic device, arranged on a support substrate, with an encapsulation cover includes, inter alia, the following sequence of steps: a) providing a support substrate on which a microelectronic device is arranged, b) depositing a bonding layer on the first face of the substrate, around the microelectronic device, c) positioning an encapsulation cover on the bonding layer in such a way as to encapsulate the microelectronic device, d) thinning the second main face of the support substrate and the second main face of the encapsulation cover by chemical etching.

A fan-out semiconductor package and packaging method thereof are disclosed. In the packaging method, a photosensitive material is used to encapsulate multiple bare chips and multiple passive devices, so multiple metal pads of each bare chip and multiple metal terminals of each passive device are exposed out of the photosensitive material by a photolithography process. The exposed metal pads and the exposed metal terminals are directly and electrically connected to a redistribution layer. In the packaging method, the bare chips and the passive devices are located on the same side of the redistribution layer and encapsulated by the photosensitive material. In addition, in the packaging method, the bare chips are not processed by a wafer bump process and does not use the thinner passive devices with high cost. Therefore, a height of the fan-out semiconductor package of the present invention is decreased and a manufacturing cost is relatively reduced.

The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height.

An encapsulated integrated circuit is provided that includes an integrated circuit (IC) die. An encapsulation material encapsulates the IC die. A phononic bandgap structure is included within the encapsulation material that is configured to have a phononic bandgap with a frequency range approximately equal to a range of frequencies of thermal phonons produced by the IC die when the IC die is operating.

Internally-shielded microelectronic packages having increased resistances to electromagnetic cross-coupling are disclosed, as are methods for fabricating such microelectronic packages. In embodiments, the internally-shielded microelectronic package includes a substrate having a frontside and a longitudinal axis. A first microelectronic device is mounted to the frontside of the substrate, while a second microelectronic device is further mounted to the frontside of the substrate and spaced from the first microelectronic device along the longitudinal axis. An internal shield structure includes or consists of a shield wall, which is positioned between the first and second microelectronic devices as taken along the longitudinal axis. The internal shield structure is at least partially composed of a magnetically-permeable material, which decreases electromagnetic cross-coupling between the first and second microelectronic devices during operation of the internally-shielded microelectronic package.

A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.

The present disclosure relates to a semiconductor package, which includes a carrier, a flip-chip die, a mold compound, and a heat spreader. Herein, the flip-chip die includes a device layer over the carrier and a die substrate over the device layer. The mold compound resides over the carrier and surrounds the flip-chip die. The mold compound has a recess adjacent to the flip-chip die, and the recess extends vertically lower than a top surface of the die substrate. The heat spreader hangs over the flip-chip die, and includes a spreader body that is thermally coupled to the die substrate, and a spreader protrusion that extends from the spreader body into the recess. A thickness of the spreader protrusion is shorter than a depth of the recess, and a width of the spreader protrusion is narrower than a width of the recess, such that the spreader protrusion is floating in the recess.

Systems and methods for manufacturing flexible electronics are described herein. Methods in accordance with embodiments of the present technology can include disposing electrical features, such as thin film circuits, on a first side of a glass substrate, applying a first protective material over the electronic features, and exposing a second side of the glass substrate to a chemical etching tank to thin the glass substrate to a predetermined thickness. The thinning process can remove cracks and other defects from the second side of the glass substrate and enhance the flexibility of the electronic assembly. A second protective material can be disposed on the second side of the thinned glass substrate to maintain the enhanced backside surface of the glass substrate. In some embodiments, the method also includes singulating the plurality of electronic features into individual electronic components by submerging the electronic assembly into a chemical etching tank.

A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.

The present disclosure relates to a semiconductor package, which includes a carrier, a flip-chip die, a mold compound, and a heat spreader. Herein, the flip-chip die includes a device layer over the carrier and a die substrate over the device layer. The mold compound resides over the carrier and surrounds the flip-chip die. The mold compound has a recess adjacent to the flip-chip die, and the recess extends vertically lower than a top surface of the die substrate. The heat spreader hangs over the flip-chip die, and includes a spreader body that is thermally coupled to the die substrate, and a spreader protrusion that extends from the spreader body into the recess. A thickness of the spreader protrusion is shorter than a depth of the recess, and a width of the spreader protrusion is narrower than a width of the recess, such that the spreader protrusion is floating in the recess.