Semiconductor structures and methods for manufacturing the same are provided. The method includes a gate structure formed over a substrate, and a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a dielectric layer formed over the S/D structure, and an S/D contact structure formed over the S/D structure. The S/D contact structure is through the dielectric layer. The semiconductor structure includes a gate contact structure formed through the dielectric layer and landing on the gate structure, and the gate contact structure is in direct contact with the gate structure. The semiconductor structure includes a bridging contact structure covering the gate contact structure and the S/D contact structure, and the bottommost surface of the bridging contact structure is in direct contact with the topmost surface of the S/D contact structure.

A photodetection module includes a photodetector and a fixing member. The photodetector includes a semiconductor substrate, a mesa portion, a first contact layer, a second contact layer, and a first electrode formed in a planar shape on a major surface of the semiconductor substrate, and electrically connected to one of the first contact layer and the second contact layer. The fixing member includes an insulating substrate, and a first wiring formed in a planar shape on a major surface of the insulating substrate. A recessed portion is formed in the major surface of the insulating substrate, and at least a part of the mesa portion is disposed inside the recessed portion. The first electrode is electrically connected to the first wiring in a state where the first electrode is in surface contact with the first wiring.

A method for manufacturing a patterned polyimide aerogel film on a substrate includes: dispensing a polyimide prepolymer sol onto a first portion of a surface of a substrate, a second portion of the surface of the substrate being substantially free of the polyimide prepolymer sol; forming a patterned film of a polyimide prepolymer gel on the substrate from the polyimide prepolymer sol; drying the polyimide prepolymer gel to form a patterned film of a polyimide prepolymer aerogel on the substrate; and curing the polyimide prepolymer aerogel on the substrate to form the patterned polyimide aerogel film on the first portion of the surface of the substrate, the second portion of the surface of the substrate being substantially free of the patterned polyimide aerogel film.

The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.

The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.

Interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the interconnects are disclosed herein. An exemplary interconnect is disposed in an insulating layer. The interconnect has a metal contact, a contact isolation layer surrounding sidewalls of the metal contact, and an air gap disposed between the contact isolation layer and the insulating layer. An air gap seal for the air gap has a first portion disposed over a top surface of the contact isolation layer, but not disposed on a top surface of the insulating layer, and a second portion disposed between the contact isolation layer and the insulating layer, such that the second portion surrounds a top portion of sidewalls of the metal contact. The air gap seal may include amorphous silicon and/or silicon oxide. The contact isolation layer may include silicon nitride. The insulating layer may include silicon oxide.

The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.

Connection with a wiring structure can be reliably achieved, whereby a semiconductor sensor device and a semiconductor sensor device manufacturing method with increased reliability are provided. A semiconductor sensor device in which a multiple of signal lines and a sensor detection portion are disposed includes a conductive film, disposed on a substrate, that configures the signal lines and whose upper face is exposed by an aperture portion of a width smaller than a width of the signal lines, a conductive member formed on the conductive film and electrically connected to the conductive film via the aperture portion, and a wiring structure, formed on an upper face of the conductive member, of an air bridge structure that connects the signal lines or the signal lines and the sensor detection portion, wherein an upper surface of the conductive member is in contact with the wiring structure, and a side face is exposed.

A manufacturing method for an air bridge structure includes forming a first photoresist structure on a substrate. The first photoresist structure includes a first opening that reveals the substrate. The manufacturing method further includes forming a bridge supporting structure on the substrate by depositing an inorganic bridge supporting material on the substrate based on the first opening in the first photoresist structure, and stripping the first photoresist structure after the deposition. Then, the manufacturing method includes forming a second photoresist structure on the substrate. The second photoresist structure includes at least a second opening that reveals at least a portion of the bridge supporting structure on the substrate. Then, the method include forming the air bridge structure by depositing an air bridge material on the substrate based on the second opening and stripping the second photoresist structure after the deposition. Further, the bridge supporting structure can be removed.

This disclosure includes a method for fabricating an air bridge, an air bridge structure, and a superconducting quantum chip, and relates to the field of circuit structures. In some examples, a method for fabricating an air bridge includes forming an air bridge brace structure on a substrate, and forming, on the air bridge brace structure and the substrate, an air bridge material layer with one or more openings in the air bridge material layer that reveal the air bridge brace structure. The air bridge material layer with the one or more openings is formed based on a patterned photoresist layer with patterns corresponding to the one or more openings. The method further includes removing, based on the one or more openings in the air bridge material layer, the air bridge brace structure to obtain the air bridge having the one or more openings.