A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.

A through-substrate vias structure includes a substrate having opposing first and second major surfaces. One or more conductive via structures are disposed extending from the first major surface to a first vertical distance within the substrate. A recessed region extends from the second major surface to a second vertical distance within the substrate and adjoining a lower surface of the conductive via. In one embodiment, the second vertical distance is greater than the first vertical distance. A conductive region is disposed within the recessed region and is configured to be in electrical and/or thermal communication with the conductive via.

Dust-sized and light transparent semiconductor chips are provided and are used in a transparent electronic system. The dust-sized and light transparent semiconductor chips are composed entirely of materials that are transparent to visible light. The dust-sized and light transparent semiconductor chips are used as a component of a transparent electronic system.

A semiconductor device includes: a first semiconductor element; a first conductor plate laminated on the first semiconductor element and connected to the first semiconductor element; a first power terminal connected to the first conductor plate, the first power terminal including a body portion extending in a first direction and a joining portion extending in a second direction different from the first direction, the joining portion being connected to the first conductor plate; and a sealing body configured to seal the first semiconductor element, the first conductor plate, the joining portion, and a part of the body portion, the sealing body having a first surface that is a surface from which the body portion projects and a second surface that is a surface placed on an opposite side of the sealing body from the first surface.

A reconstituted wafer includes a plurality of apertures defined in a first substrate. A module is positioned in each aperture and coupled to circuit traces on the first substrate by operation of beam leads extending from the module. A second substrate is positioned over the first substrate and each module is hermetically sealed in a space defined by the respective aperture and the second substrate. One or more vias are provided to access I/O signals at a surface of the first or second substrates. The modules may include an invariant die where different technologies are stacked together.

A packaged semiconductor device has a plurality of leads. A respective lead is to be welded to an electrical coupling that has a substantially rectangular end section. The end section has a width that is greater than a width of the respective lead. The respective lead is aligned within the width of the end section, such that the respective lead extends in a direction substantially perpendicular to the width of the end section. With the respective lead and the end section aligned, the respective lead is welded to the end section.

Provided is a semiconductor device enabling highly accurate adjustment of a mounting height at a time when the semiconductor device is mounted on an assembly board, and an electronic apparatus. A linear lead is extracted from a bottom surface of a cylindrical resin sealing body covering a semiconductor chip, and a plurality of helical leads are arranged so as to wind around the linear lead, to thereby form a multi-helical structure. The plurality of helical leads forming the multi-helical structure has the same pitch.

A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.

A packaged semiconductor device has a plurality of leads. A respective lead is to be welded to an electrical coupling that has a substantially rectangular end section. The end section has a width that is greater than a width of the respective lead. The respective lead is aligned within the width of the end section, such that the respective lead extends in a direction substantially perpendicular to the width of the end section. With the respective lead and the end section aligned, the respective lead is welded to the end section.

A semiconductor device has a first semiconductor wafer. The first semiconductor wafer is singulated to provide a first wafer section including at least one first semiconductor die or a plurality of first semiconductor die. The first wafer section is a fractional portion of the first semiconductor wafer. An edge support structure is formed around the first wafer section. A second wafer section includes at least one second semiconductor die. The second wafer section can be an entire second semiconductor wafer. The first semiconductor die is a first type of semiconductor device and the second semiconductor die is a second type of semiconductor device. An alignment opening is formed through the first wafer section and second wafer section with a light source projected through the opening. The first wafer section is bonded to the second wafer section with the first semiconductor die aligned with the second semiconductor die.