Provided is a semiconductor device enabling highly accurate adjustment of a mounting height at a time when the semiconductor device is mounted on an assembly board, and an electronic apparatus. A linear lead is extracted from a bottom surface of a cylindrical resin sealing body covering a semiconductor chip, and a plurality of helical leads are arranged so as to wind around the linear lead, to thereby form a multi-helical structure. The plurality of helical leads forming the multi-helical structure has the same pitch.

A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

A through-substrate via structure includes a conductive via structure including trench portions at a first major surface of a substrate and extending to a first distance. A first insulating structure is over sidewalls of the trench portions, and a conductive material is over the first insulating structure. A recessed region extends from a second major surface of the substrate to a second distance greater than the first distance and laterally overlaps and interfaces both trench portions. A second insulating structure includes a first portion within the recessed region and a second portion adjacent to the second major surface outside of the recessed region, which includes an outer surface overlapping the second major surface outside of the recessed region. A first conductive region includes a proximate end coupled to the conductive material through openings in the first portion, and an opposite distal that is outward from the second portion.

A through-substrate vias structure includes a substrate having opposing first and second major surfaces. One or more conductive via structures are disposed extending from the first major surface to a first vertical distance within the substrate. A recessed region extends from the second major surface to a second vertical distance within the substrate and adjoining a lower surface of the conductive via. In one embodiment, the second vertical distance is greater than the first vertical distance. A conductive region is disposed within the recessed region and is configured to be in electrical and/or thermal communication with the conductive via.

A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.

A semiconductor module includes: a first substrate having a first insulating substrate and a first conductor layer; a power device part having a first electrode, a second electrode and a gate electrode; a second substrate having a second insulating substrate, a second conductor layer and a third conductor layer wherein a hole is formed in the second insulating substrate, the second conductor layer has a bonding portion and a surrounding wall portion; an inner resin portion; a control IC; and an outer resin portion, wherein the first substrate, the power device part, the second substrate and the control IC are stacked in this order, a connector is disposed in the inside of the hole, and the gate electrode is electrically connected to a control signal output terminal of the control IC through a connector.

A through-substrate via structure includes a conductive via structure including trench portions at a first major surface of a substrate and extending to a first distance. A first insulating structure is over sidewalls of the trench portions, and a conductive material is over the first insulating structure. A recessed region extends from a second major surface of the substrate to a second distance greater than the first distance and laterally overlaps and interfaces both trench portions. A second insulating structure includes a first portion within the recessed region and a second portion adjacent to the second major surface outside of the recessed region, which includes an outer surface overlapping the second major surface outside of the recessed region. A first conductive region includes a proximate end coupled to the conductive material through openings in the first portion, and an opposite distal that is outward from the second portion.

A method for removing material from a substrate includes providing the substrate with first and second opposing major surfaces. A masking layer is disposed along one of the first major surface and the second major surface, and is provided with a plurality of openings. The substrate is placed within an etching apparatus and material is removed from the substrate through openings using the etching apparatus. The thickness of the substrate is measured within the etching apparatus using a thickness transducer. The measured thickness is compared to a predetermined thickness and the material removal step is terminated responsive to the measured thickness corresponding to the predetermined thickness. In one embodiment, the method is used to more accurately form recessed regions in semiconductor die, which can be used in, for example, stacked device configurations.

A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.

A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.