A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer. The conductive pad has a first portion passing through the insulating layer and the barrier layer and connected to the conductive via structure. The chip package structure includes a conductive bump over the conductive pad. The chip package structure includes a second substrate. The chip package structure includes an underfill layer between the first substrate and the second substrate.

According to one embodiment, a semiconductor device includes: a semiconductor layer including a first plane extending along a plane including a first axis and a second axis; a first electrode extending along the first axis; a second electrode extending along the second axis; and a third electrode above the first plane. The third electrode is electrically coupled to the first electrode and the second electrode, and includes a first portion, a second portion and a third portion. The first portion crosses the first electrode. The second portion crosses the second electrode. The third portion crosses the second electrode and is separate at a first end from the second portion.

A device includes trenches. The trenches each include a conductive element configured to electrically couple coupling fingers of transistor gates located on a first side of a first layer, to a second layer extending on the side of a second face of the first layer.

A semiconductor device includes a substrate, a channel layer provided on the substrate, a semiconductor layer provided on the channel layer, gate fingers and a gate connection wiring provided on the semiconductor layer, and an insulating film provided between the semiconductor layer and the gate fingers, wherein the gate fingers includes a first gate finger, and a second gate finger closer to the center of the gate fingers in an arrangement direction than the first gate finger, wherein a first distance between a lower surface of the first gate finger in contact with the insulating film and an upper surface of the channel layer in contact with the semiconductor layer is greater than a second distance between a lower surface of the second gate finger in contact with the insulating film and the upper surface of the channel layer in contact with the semiconductor layer.

A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The semiconductor device further has a polymeric material disposed over the semiconductor substrate and surrounding the conductor. The semiconductor device also includes an electric conductive layer between the conductor and the polymeric material. In the semiconductor device, an adhesion strength between the electric conductive layer and the polymeric material is greater than an adhesion strength between the polymeric material and the conductor.

A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically conducting or doped semiconductor substrate is provided. A metalization of source electrode contact areas, a metalization of drain electrode contact areas and a metalization of gate electrode contact areas are on a semiconductor surface of the semiconductor layers and have a plurality of metalization layers, between which insulation layers are arranged in a lateral direction. The metalization layers both for the source electrode metalization and for the drain electrode metalization have a comb structure with contact fingers. The contact fingers of the source electrode metalization and of the drain electrode metalization intermesh in a spaced-apart fashion and each contact finger has a contact finger foot and a contact finger tip. A width of the contact finger foot is greater than a width of the contact finger tip.

A semiconductor device includes a first semiconductor region of a first conductive type, a second semiconductor region of a second conductive type, a first electrode, a third semiconductor region of the second conductive type, a fourth semiconductor region of the first conductive type, and a conductive portion. The second semiconductor region is provided on the first semiconductor region. The first electrode is provided on the second semiconductor region. The third semiconductor region is provided on the first electrode. The fourth semiconductor region is provided on the third semiconductor region. The conductive portion is surrounded by the third semiconductor region and an intervening insulation portion and is electrically connected to the first electrode.

Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

A semiconductor device includes a device region including a compound semiconductor material and a non-device region at least partially surrounding the device region. The semiconductor device further includes a dielectric material in the non-device region and at least one electrode in the device region. The semiconductor device further includes at least one pad electrically coupled to the at least one electrode, wherein the at least one pad is arranged on the dielectric material in the non-device region.