A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The semiconductor device further has a polymeric material disposed over the semiconductor substrate and surrounding the conductor. The semiconductor device also includes an electric conductive layer between the conductor and the polymeric material. In the semiconductor device, an adhesion strength between the electric conductive layer and the polymeric material is greater than an adhesion strength between the polymeric material and the conductor.

In an embodiment, an electronic component includes a dielectric core layer having a first major surface, a semiconductor die embedded in the dielectric core layer, and a first conductive layer. The semiconductor die includes a first major surface and at least two conductive fingers arranged on the first major surface which are coupled to a common potential. The first conductive layer is arranged on, and electrically coupled to, the at least two conductive fingers and extends from the at least two conductive fingers over the first major surface of the dielectric core layer.

A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region.

A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (LDMOS) cells. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metallic pillars distributed over and electrically coupled to the redistribution layer.

A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.

A transistor includes: a semiconductor substrate; a plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes on the semiconductor substrate; a drain pad on the semiconductor substrate and connected to the plurality of drain electrodes; a metal wiring on the semiconductor substrate and arranged spaced apart from, adjacent to and parallel to the drain pad; and a ground pad on the semiconductor substrate and connected to both ends of the metal wiring.

A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.

A semiconductor device includes a semiconductor substrate; an active element configured to be formed on the semiconductor substrate; and a multi-layer wiring structure configured to be formed on the semiconductor substrate. A heat dissipation structure is provided in the multi-layer wiring structure. The upper end of the heat dissipation structure forms an external connection pad to be connected with an external wiring board, and the lower end of the heat dissipation structure makes contact with a surface of the semiconductor substrate outside of an element forming region for the active element.

A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain stripe. The power transistor also includes multiple substantially parallel conductive connection lines, where each conductive connection line connects at least one source stripe to a common source connection or at least one drain stripe to a common drain connection. The conductive connection lines are disposed substantially perpendicular to the transistor fingers. At least one of the source or drain stripes is segmented into multiple portions, where adjacent portions are separated by a cut location having a higher electrical resistance than remaining portions of the at least one segmented source or drain stripe.

The present disclosure relates to an integrated chip packaging device. In some embodiments, the packaging device has a first package component. A metal trace is arranged on a surface of the first package component. The metal trace has an undercut. A molding material fills the undercut of the metal trace and has a sloped outermost sidewall with a height that monotonically decreases from a position below a top surface of the metal trace to the surface of the first package component. A solder region is arranged over the metal trace.