A device structure is formed using a silicon-on-insulator substrate. The device structure includes a first switch and a second switch that are formed using a device layer of the silicon-on-insulator substrate. A trap-rich layer is between a substrate and a buried insulator layer of the silicon on-insulator substrate. An electrically-conducting connection is located in a trench extending from the device layer through the buried insulator layer to the trap-rich layer such that the electrically-conducting connection is coupled with the substrate. The electrically-conducting connection at least partially comprised of trap-rich material.

A semiconductor package structure includes a first dielectric layer, a conductive element, a first circuit structure, a semiconductor die and an encapsulant. The first dielectric layer defines at least one through hole. The conductive element is disposed in the through hole and including a first portion and a second portion. A first surface of the first portion is substantially coplanar with a first surface of the first dielectric layer, and a portion of a first surface of the second portion is recessed from the first surface of the first dielectric layer. The first circuit structure is disposed on the first dielectric layer. The semiconductor die is electrically connected to the first circuit structure. The encapsulant covers the semiconductor die.

Semiconductor devices may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Methods of making semiconductor devices may involve supporting a backside-biased semiconductor die supported above a substrate, a backside surface of the backside-biased semiconductor die being spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Systems may include a sensor device, a nontransitory memory device, and at least one semiconductor device operatively connected thereto. The at least one semiconductor device may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be electrically connected to ground by wire bonds extending to the substrate.

A semiconductor device including a biosensor with an on-chip reference electrode embedded within the semiconductor device, and associated manufacturing methods are provided. In some embodiments, a pair of source/drain regions is disposed within a device substrate and separated by a channel region. An isolation layer is disposed over the device substrate. A sensing well is disposed from an upper surface of the isolation layer overlying the channel region. A bio-sensing film is disposed along the upper surface of the isolation layer and extended along sidewall and lower surfaces of the sensing well. A reference electrode is disposed vertically between the bio-sensing film and the isolation layer.

A stacked field-effect transistor (FET) switch is disclosed. The stacked FET switch has a first FET device stack that is operable in an on-state and in an off-state and is made up of a first plurality of FET devices coupled in series between a first port and a second port, wherein the first FET device stack has a conductance that decreases with increasing voltage between the first port and the second port. The stacked FET switch also includes a second FET device stack that is operable in the on-state and in the off-state and is made up of a second plurality of FET devices coupled in series between the first port and the second port, wherein the second FET device stack has a conductance that increases with increasing voltage between the first port and the second port.

There is provided a semiconductor device including a multi-gate transistor having a plurality of gates in a common active region, in which the multi-gate transistor has a comb-shaped metal structure in which a first metal is drawn out and bundled in a W length direction from contacts arranged in a single row in each of a source region and a drain region, and the multi-gate transistor has a wiring layout in which a root section of the first metal coincides immediately above an end of the source region and the drain region or is disposed inside the end of the source region and the drain region in the W length direction.

A semiconductor package includes a leadframe including leads and a die attach pad (DAP) inside the leads, and at least one semiconductor die having a top side including circuitry electrically connected to bond pads and a bottom side attached to a bottom side portion of the DAP. The package includes a mold compound and a heat slug having a top side and a bottom side positioned within a cavity defined by sidewalls of the mold compound. The heat slug has an area greater than an area of the DAP is attached by its bottom side with a thermally conductive adhesive material to a top side portion of the DAP. Bondwires are between the leads and the bond pads. Exposed from the mold compound is a bottom side surfaces of the leads and the top side of the heat slug.

According to one embodiment, a semiconductor device includes first to sixth semiconductor regions, a first electrode, and a first insulating film. The first semiconductor region includes first and second partial regions. The second semiconductor region is separated from the first partial region in a second direction crossing a first direction. The third semiconductor region is provided between the first partial region and the second semiconductor region. The fourth semiconductor region is provided between the first partial region and the third semiconductor region. The first electrode is separated from the second partial region, the second and third semiconductor regions, and a portion of the fourth semiconductor region. The first insulating film contacts the third semiconductor region. The fifth semiconductor region is provided between the first insulating film and the second partial region. The sixth semiconductor region is provided between the first insulating film and the fifth semiconductor region.

A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming a first switch and a second switch in the device layer. An electrically-conducting connection is formed in a trench. The handle wafer is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.

A device structure with a backside contact includes a silicon-on-insulator substrate including a device layer, a buried insulator layer, and an electrically-conducting connection in a trench. A final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.