In one implementation, a method for forming ultra-thin semiconductor components includes fabricating multiple devices including a first device and a second device in a semiconductor wafer, and forming a street trench within the semiconductor wafer and between the first and second devices. The method continues with forming a dielectric skeleton structure over the semiconductor wafer, the dielectric skeleton structure laterally extending to at least partially cover the first and second devices, while also substantially filling the street trench. The method continues with thinning the semiconductor wafer from a backside to expose the dielectric skeleton structure in the street trench to form a first ultra-thin semiconductor component having the first device, and a second ultra-thin semiconductor component having the second device. The method can conclude with cutting through the dielectric skeleton structure to singulate the first and second ultra-thin semiconductor components.

An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated device includes a set of contact terminals for contacting the integrated circuit. At least one contact terminal of said set of contact terminals includes a contact layer of metal material being suitable to be directly coupled mechanically to an element external to the chip, and a coupling element for improving an electrical and/or mechanical coupling between the contact layer and the chip. The coupling element includes a coupling layer being formed by a combination between the metal material of the contact layer and the semiconductor material of the chip, with the coupling layer that is directly coupled to the chip and to the contact layer.

A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming a first switch and a second switch in the device layer. A trench that extends through the device layer and partially through the buried insulator layer is formed. An electrically-conducting connection is formed in the trench.

A solder joint in which an electronic component with a back metal is bonded to a substrate by a solder alloy. The solder alloy includes: a solder alloy layer having an alloy composition consisting of, in mass %: Ag: 2 to 4%, Cu: 0.6 to 2%, Sb: 9.0 to 12%, Ni: 0.005 to 1%, optionally Co: 0.2% or less and Fe: 0.1% or less, with the balance being Sn; an SnSb intermetallic compound phase; a back metal-side intermetallic compound layer formed at an interface between the back metal and the solder alloy; and a substrate-side intermetallic compound layer formed at an interface between the substrate and the solder alloy. The solder alloy layer exists at least one of between the SnSb intermetallic compound phase and the back metal-side intermetallic compound layer, and between the SnSb intermetallic compound phase and the substrate-side intermetallic compound layer.

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first chip, a second chip, self-aligned structures, a bridge structure, and an insulating encapsulant. The first chip has a first rear surface opposite to a first active surface. The second chip is disposed beside the first chip and has a second rear surface opposite to a second active surface. The self-aligned structures are disposed on the first rear surface of the first chip and the second rear surface of the second chip. The bridge structure is electrically connected to the first chip and the second chip. The insulating encapsulant covers at least the side surfaces of the first and second chips, a side surface of the semiconductor substrate, and the side surfaces of the self-aligned structures.

Implementations of a method of making a plurality of alignment marks on a wafer may include: providing a wafer including an alignment feature on a first side of the wafer. The method may include aligning the wafer using a camera focused on the first side of the wafer. The wafer may be aligned using the alignment feature on the first side of the die. The wafer may also include creating a plurality of alignment marks on a second side of the wafer through lasering, sawing, or scribing.

Implementations of methods of singulating a plurality of die included in a substrate may include forming a groove through a backside metal layer through laser ablating a backside metal layer at a die street of a substrate and singulating a plurality of die included in the substrate through removing substrate material of the substrate in the die street.

The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A power module includes a first terminal, a second terminal, and a number of semiconductor die coupled between the first terminal and the second terminal. The semiconductor die are configured to provide a low-resistance path for current flow from the first terminal to the second terminal during a forward conduction mode of operation and a high-resistance path for current flow from the first terminal to the second terminal during a forward blocking configuration. Due to improvements made to the power module, it is able to pass a temperature, humidity, and bias test at 80% of its rated voltage for at least 1000 hours.