A package comprises a platform and at least one pedestal positioned along at least a portion of a perimeter of the platform. The platform and the at least one pedestal form a cavity. The package further comprises a die positioned in the cavity and on the platform, with the die having an active circuit facing away from the platform. The package also comprises a conductive layer coupled to the die and to a conductive terminal. The conductive terminal is positioned above the at least one pedestal, and the die and the conductive terminal are positioned in different horizontal planes.

A manufacturing method of a semiconductor package includes the following steps. A chip is provided. The chip has an active surface and a rear surface opposite to the active surface. The chip includes conductive pads disposed at the active surface. A first solder-containing alloy layer is formed on the rear surface of the chip. A second solder-containing alloy layer is formed on a surface and at a location where the chip is to be attached. The chip is mounted to the surface and the first solder-containing alloy layer is aligned with the second solder-containing alloy layer. A reflow step is performed on the first and second solder-containing alloy layers to form a joint alloy layer between the chip and the surface.

An electric connection is provided, and has a first copper (Cu) layer, a second Cu layer, and a composite metal layer disposed between the first Cu layer and the second Cu layer. The composite metal layer has 0.01 wt. %gallium (Ga)20 wt. %, 0.01 wt. %copper (Cu)50 wt. %, and 30 wt. %nickel (Ni)99.98 wt. %. Moreover, a method of manufacturing the electric connection is provided, and has the steps of: (1) providing a first Cu layer and a second Cu layer; (2) forming a first Ni layer on the first Cu layer; (3) forming a second Ni layer on the second Cu layer; (4) forming a Ga layer on the first Ni layer; and (5) keeping the second Ni layer in contact with the Ga layer and carrying out a thermo-compress bonding therebetween to form the electric connection.

An apparatus for bonding die to a board includes a circuit board having a solderable layer and a plurality of die bonded to the circuit board using at least three respective layers. Each of the at least three respective layers includes an inner layer, a first alloy of material from an outer layer and the solderable layer of the circuit board, and a second alloy of material from the outer layer and the solderable layer of the circuit board. Melting temperatures of the first alloy and the second alloy are higher than reflow temperatures of the outer layer and the solderable layer of the circuit board.

A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.

The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

The present disclosure relates to a high-power acoustic device with improved performance. The disclosed acoustic device includes a substrate, a die-attach material, and an acoustic die. The substrate includes a substrate body and a die pad on a top surface of the substrate body. The die-attach material is a sintered material and applied over the die pad. The acoustic die is coupled to the die pad via the die-attach material. Herein, the acoustic die includes a die body and a metallization structure, which is sandwiched between the die body and the die-attach material.

A power module includes a first terminal, a second terminal, and a number of semiconductor die coupled between the first terminal and the second terminal. The semiconductor die are configured to provide a low-resistance path for current flow from the first terminal to the second terminal during a forward conduction mode of operation and a high-resistance path for current flow from the first terminal to the second terminal during a forward blocking configuration. Due to improvements made to the power module, it is able to pass a temperature, humidity, and bias test at 80% of its rated voltage for at least 1000 hours.

When a defect region is present near the pn junction in a GaN layer, lattice defects are present in the depletion layer. Therefore, when a reverse bias is applied to the pn junction, the defects in the depletion layer cause the generated current to flow as a leakage current. The leakage current flowing through the depletion layer can cause a decrease in the withstand voltage at the pn junction. Provided is a semiconductor device using gallium nitride, including a gallium nitride layer including an n-type region. The gallium nitride layer includes a first p-type well region and a second p-type well region that is provided on at least a portion of the first p-type well region and has a peak region with a higher p-type impurity concentration than the first p-type well region.