A method for a method of forming a semiconductor device includes providing a semiconductor substrate having a bottom surface opposite a top surface with circuitry disposed at the top surface. The method further includes forming a first metal layer having a first metal over the bottom surface of the semiconductor substrate. The first metal layer is formed by depositing an adhesion promoter followed by depositing the first metal.

An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated device includes a set of contact terminals for contacting the integrated circuit. At least one contact terminal of said set of contact terminals includes a contact layer of metal material being suitable to be directly coupled mechanically to an element external to the chip, and a coupling element for improving an electrical and/or mechanical coupling between the contact layer and the chip. The coupling element includes a coupling layer being formed by a combination between the metal material of the contact layer and the semiconductor material of the chip, with the coupling layer that is directly coupled to the chip and to the contact layer.

A wiring substrate includes insulating layers including a first insulating layer and an outermost insulating layer such that the first insulating layer is positioned at one end of the insulating layers in a lamination direction and that the outermost insulating layer is positioned at the opposite end of the insulating layers in the lamination direction and includes a reinforcing material; conductive layers laminated on the insulating layers such that the conductive layers include an outermost conductive layer formed on the outermost insulating layer and including pads, and a semiconductor element accommodated in an accommodating portion of the first insulating layer. The insulating layers are formed such that the insulating layers do not contain a reinforcing material other than the outermost insulating layer.

A method for manufacturing a semiconductor device includes preparing a semiconductor chip having a back surface made of a Cu layer. The semiconductor chip is bonded to a die pad having a front surface made of Cu via a bonding material containing a dissimilar metal not containing Cu and Pb and a Bi-based material so that the Cu layer and the bonding material come into contact with each other. After the bonding, the die pad is then heat-treated.

An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated device includes a set of contact terminals for contacting the integrated circuit. At least one contact terminal of said set of contact terminals includes a contact layer of metal material being suitable to be directly coupled mechanically to an element external to the chip, and a coupling element for improving an electrical and/or mechanical coupling between the contact layer and the chip. The coupling element includes a coupling layer being formed by a combination between the metal material of the contact layer and the semiconductor material of the chip, with the coupling layer that is directly coupled to the chip and to the contact layer.

A stacked structure comprises a semiconductor chip which includes a substrate having at least one substrate via hole penetrating through the substrate; at least one backside metal layer formed on a backside of the substrate covering an inner surface of the substrate via hole and at least part of the backside of the substrate; at least one front-side metal layer formed on the front-side of the substrate and electrically connected to the at least one backside metal layer on a top of at least one of the at least one substrate via hole; at least one electronic device formed on the front-side of the substrate and electrically connected to the at least one front-side metal layer; and at least one metal bump formed on at least one of the backside metal layer and the front-side metal layer.

A semiconductor device according to the present invention, having an Au-based solder layer (3) sandwiched between a semiconductor element (1) and a Cu substrate (2) made mainly of Cu, in which the semiconductor device includes: a dense metal film (23) which is arranged between the Cu substrate (2) and the Au-based solder layer (3), and has fine slits (24) patterned to have a predetermined shape in a plan view; and fine structures (4) with dumbbell-like cross section, which have Cu and Au as main elements, and are each buried in the Cu substrate (2), the Au-based solder layer (3), and the fine slits (24) of the dense metal film (23).

A fan-out semiconductor package includes a semiconductor chip including a body and an electrode pad disposed on the body, a metal layer disposed on the electrode pad of the semiconductor chip, and a interconnection member including an insulating layer disposed on one side of the semiconductor chip, a via hole penetrating through the insulating layer and exposing at least a portion of a surface of the metal layer, a seed layer disposed on the surface of the metal layer exposed by the via hole and a wall of the via hole, and a conductor layer disposed on the seed layer.

A semiconductor package includes semiconductor bridge, first and second multilayered structures, first encapsulant, and a pair of semiconductor dies. Semiconductor dies of the pair include semiconductor substrate and conductive pads disposed at front surface of semiconductor substrate. Semiconductor bridge electrically interconnects the pair of semiconductor dies. First multilayered structure is disposed on rear surface of one semiconductor die. Second multilayered structure is disposed on rear surface of the other semiconductor die. First encapsulant laterally wraps first multilayered structure, second multilayered structure and the pair of semiconductor dies. Each one of first multilayered structure and second multilayered structure includes a top metal layer, a bottom metal layer, and an intermetallic layer. Each one of first multilayered structure and second multilayered structure has surface coplanar with surface of first encapsulant. The top metal layers, the bottom metal layers, and the intermetallic layers are in contact with the first encapsulant.

Provided is an adhesive tape for a semiconductor package manufacturing process. The adhesive type includes: a first adhesive layer formed on a first base film; a second base film formed on the first adhesive layer, in which the second base film changes its shape to conform to the topology of the semiconductor package bottom surface when the adhesive tape is attached to the semiconductor package bottom surface, and containing a metal element so as to independently maintain the changed shape during the process; and a second adhesive layer formed on the second base film, the second adhesive layer having a smaller thickness than the first adhesive layer and having a lower adhesive strength than the first adhesive layer, wherein each of the first adhesive layer and the second adhesive layer has a spiral network molecular structure and includes a first adhesive composition containing silicone.