A semiconductor device including source/drain contacts extending into source/drain regions, below topmost surfaces of the source/drain regions, and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a first gate stack over the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source/drain region adjacent the first gate stack and the first channel region; and a first source/drain contact coupled to the first epitaxial source/drain region, a bottommost surface of the first source/drain contact extending below a topmost surface of the first channel region.

In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

A semiconductor structure includes first and second source/drain (S/D) features, one or more semiconductor channel layers connecting the first and second S/D features, a gate structure engaging the one or more semiconductor channel layers, a metal wiring layer at a backside of the semiconductor structure, an S/D contact electrically connecting the first S/D feature to the metal wiring layer, and a seal layer between the metal wiring layer and the gate structure. The seal layer is spaced away from the gate structure by an air gap therebetween.

In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.

Embodiments of the present disclosure provide a semiconductor package comprising a first integrated circuit (IC) die having a first back-end-of-the-line (BEOL) structure, a second integrated circuit die having a second BEOL structure, an integrated BEOL structure having a first side in direct contact with both the first BEOL structure and the second BEOL structure. In some embodiments, a substrate is further disposed at a second side of the integrated BEOL structure to support both the first integrated circuit die and the second integrated circuit die.

Embodiments of the present disclosure provide a semiconductor package comprising a first integrated circuit (IC) die having a first back-end-of-the-line (BEOL) structure, a second integrated circuit die having a second BEOL structure, an integrated BEOL structure having a first side in direct contact with both the first BEOL structure and the second BEOL structure. In some embodiments, a substrate is further disposed at a second side of the integrated BEOL structure to support both the first integrated circuit die and the second integrated circuit die.

Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.

Embodiments include a contact structure and method of forming the same where the contact structure is deliberately positioned near the end of a metallic line. An opening is formed in an insulating structure positioned over the metallic line and then the opening is extended into the metallic line by an etching process. In the etching process, the line end forces etchant to concentrate back away from the line end, causing lateral etching of the extended opening. A subsequent contact is formed in the opening and enlarged opening.

The present disclosure relates to a manufacturing method of a semiconductor structure, including: the base includes an array region and a peripheral region a depth of the TSV is smaller than a thickness of the base; forming a filling dielectric layer; forming a conductive layer in the TSV, the conductive layer is flush with an upper surface of the filling dielectric layer; forming first metal layers an upper surface of each of the first metal layers is flush with an upper surface of the conductive layer; forming a first dielectric layer; and forming a first interconnection structure and second interconnection structures at the same time in the first dielectric layer, a bottom of the first interconnection structure is in contact with one of the first metal layers, and bottoms of the second interconnection structures are in contact with the conductive layer.

A method for manufacturing a semiconductor structure, including: providing a base; forming a Through Silicon Via (TSV) in the base, with a depth of the TSV being less than a thickness of the base; and forming a liner layer on a sidewall and the bottom of the TSV, and forming a conductive layer in the TSV, the liner layer including a polish-stop layer.